ddr frequency for 2GQ/~3A5/~3B4.
2. Add example code to specify wrlvl_dq_dly separately when enable ARB_LEVEL in 3a780e branch.
3. Modify the PMON print MC parameter format to print the address.
Change-Id: Ic240f2f9ddb0272883aba393d687b3e47abe51e7
Originally the frequency of the I2C0 Controller
is too high to access the eeprom of ddr correctly.
Now adjust it under 100K, it is in I2C's normal
range.
Target: 3a2h 2gq2h
when start pmon on 3a2h/2gq2h it can not press the "Delete" key
enter to setup BIOS interface or can enter to setup BIOS interface
but not quit,Now fixed it you can press the "Delete" key enter to
setup BIOS interface and can quit success.
Target:Bonito3a2h Bonito2gq2h
Present ls2h ddr initialize is slower than ls2GQ ddr initialize,
when ls2GQ to init dc and user framebuffer but ls2h ddr
initialization has not completed, this will cause display huaping
when start pmon,Now add a waiting time for ls2h ddr initialize.
Target:Bonito2gq2h
Now we store arb leveled info seperately for each MC(up to 4 MC, tow 3A/B).
If the CLKSEL pin(DDR frequency) or DIMMs is changed, then we will do arb level
again.
Branch Bonito3a/b780e, Bonito3a/bserver, Bonito3a2h, Bonito2gq2h/780e is updated.
Now on 2GQ2H board you can judge NIC work mode is 100Mbps or 1000Mbps by
see network port led color display.(100Mbps LED is green 1000Mbps LED is
orange)
Target:Bonito2gq2h
This patch is used to fix ls2h HT controler bug which will cause
ls3a/ls2gq and ls2h HT connection fail.
Notice: ls2h bios should has corresponding code to support this patch
Thanks <wanghuandong@loongson.cn>
Target: Bonito3a2h Bontio2gq2h
Chen Xinke
Chenming
huang pei
liushaozong
Zhang Lihong
XiaQichao