3cserver, 3c780 and 3aserver
*. pcitlb.S mapped 33 instead of 32 tlb entry, the 33th of which mapped
cpu address 0x0 ~ 0x2000000 to physical address 0x8000 0000 ~ 0x8200 0000.
This COVERS NULL reference
*. ehci device was not enabled, so did not get bar initialized
during PCI bus enumeration
*. value in BAR0 is PCI address space, when need CPU address
tranformation
Change-Id: I576534bf61c7cd374dc2917454b8818e793851a6
ddr frequency for 2GQ/~3A5/~3B4.
2. Add example code to specify wrlvl_dq_dly separately when enable ARB_LEVEL in 3a780e branch.
3. Modify the PMON print MC parameter format to print the address.
Change-Id: Ic240f2f9ddb0272883aba393d687b3e47abe51e7
*. 3a780e, 3aserver, 3c780e and 3cserver all use core 0 as BP
and boot all other core, this is compatiable to previous version;
*. When changing the BOOTCORE_ID and/or RESERVED_COREMASK, you
NEED "make cfg", to let it take effect
Change-Id: I8d6485407408baa969fce4f5473cabc4c2ee40af
the cause is the DMA request from 0xfe000000 ~ 0xff000000 is intercepted
and mistaken as MSI interrupt by the RS780E HT/PCI controller. Now exclude
this area for dma;
Change-Id: Ie8a61ee28d0b1d0ed23b2cfa5fa34fe820bbd56d
It displays in three plays:pmon bios, before pmon command line, `sysinfo mem` command. Now all of them are right.
Change-Id: I6eaf42f3df83a2603decf32cfea131a84f773374
In this commit, when we pass emap entry with mem_size < 1MB, we set bit31 to 1
in mem_size to indicate the value in bit30~bit0 is Byte in unit, not MByte
2. Set default wr_dq_dly from 0x20 to 0x1c.
3. Update ARB level to better support reduc data width mode.
4. Update 3a780e DDR3 UDIMM parameters(305M stable with 1 kingston 2GB DIMM at each MC--DIMM1/2).
5. Enable MC Interleave mode when each MC has 1GB, 2GB, 4GB(3A2H only) capacity.
Targets: Bonito3a*
According to the NB's rpr mannual, to initial the GFX and GPP bus, the
training bit must be clear otherwise th NB training function couldn't
work normally.
The old code's GFX&GPP initial branch was improper because the bit didn't clear;
The patch cleared the bit to made the branch run correctly.
Target: Bonito3a780e & Bonito3aserver
The bus(GFX-port0) couldn't use RAID Adpter on the 3A-TWOWAY motherboard.
The patch fixed it by debugging the bus2's initial source code.
Target: Bonito3aserver
Before if the pci device is not a multi-function device,it will still
initialize as a multi-function,Now fix it.
Target:Bonito3a780e Bonito3aserver Bonito3b780e Bonito3bserver
Bonito3c780e Bonito3cserver
Now we store arb leveled info seperately for each MC(up to 4 MC, tow 3A/B).
If the CLKSEL pin(DDR frequency) or DIMMs is changed, then we will do arb level
again.
Branch Bonito3a/b780e, Bonito3a/bserver, Bonito3a2h, Bonito2gq2h/780e is updated.
Before:The SATA GEN II PHY port output was 650mv, but the Signal quality was bad.
Now:The Signal quality is better when the SATA GEN II PHY port output is set to 600 mv.
Target: 3Aserver
Now the type 16 of smbios support Physical Memory Array and the type 17 of smbios
support Memory Device.
Targets: Bonito3aserver Bonito3a780e Bonito3b780e
1.when ohci1 has USB KBD and after bmc boot, pmon booting ,usb kbd can't work.
2.sb700_usb.c fixed usb hub can't work in systerm.
Targets: Bonito3aserver
When you use AST2050' VGA,you should open USE_BMC and VGA_BASE=0xb4000000 options.
Default:
rs780e vga option has been open:
USE_780E_VGA
VGA_BASE=0xbe000000
Targets: Bonito3aserver
Before the time of scan "Del" button is too short,
resulted into set the bios of the interface.Now
extended the time of the scan "Del" button.But in
order to improve the bios of the start-up time,this
option is off by default.
Target:Bonito3a780e Bonito3aserver Bonito3b780e Bonito3bserver
Bonito3c780e Bonito2gq780e Bonito3a2h
Before when run the pmon the node0 have memory or no memory makes no
difference,Now add a beep when the node0 no memory.
Target:Bonito3a780e Bonito3aserver
Original code asume pci/pcie multi-function devices share the same
interrupt line, and assign the same irq number for multi-function.
Infatc, different irq line is used between pci/pcie multi-function
devices to speed up interrupt response. Now neighboure interrupt
line attached to PIC is used, new irq number is deliveried to
multi-function pci/pcie devices. It pass test on ls3a780e board
with a multi-function card which integrated video and HDA function.
NOTICE: assume interrupt route register(offset:0x3D) of multi-funciont
pci card is default configured.
Target:all
Original code has no test command support in PMON command line, it caused the problem as Bug 353
described as http://www.loongson.cn/dev/bugzilla/show_bug.cgi?id=353 showes. Now the command
is added for Bonito3aserver.
Targets: Bonito3aserver
Original code didn't dump "t8" and "t9" regiser, but client programm
need to dump "t8" and "t9". Now the function is added, and pass test
on ls3b780e board. Thanks <wanghuandong@loongson.cn>
NOTICE: user should update its ejtag client programm on x86 to match
this patch by command "git clone git://10.2.5.27/ejtag.git",otherwise
incorrect value maybe got during dump some cp0 register.
Target:Bonito3a780e,Bonito3b780e,Bonito3aserver,Bonito3bserver,Bonito3c780e
Original code made a misstake which use "==" instead of "=" during
checking interrupt line register value, however it doesn't affect
system interrupt number routing. Now all the code is changed.
Target:Bonito3a780e,Bonito3b780e,Bonito3aserver,Bonito3bserver,Bonito3c780e
Original code use register "a0" to store ejtag address for dump tlb
registers, but "a0" hasn't been saved before it's used. Now use "t2"
instead of "a0", because "t2" has been saved in stack on x86 memory.
Thanks wanghuandong@loongson.cn
Target:Bonito3a780e,Bonito3b780e,Bonito3c780e,Bonito3aserver,Bonito3bserver
lixuefeng
Huang Pei
Chen Xinke
Chenming
Huang Pei
HUO Wenyang
Zhang Lihong
meiwenbin
fandongdong
Wang Huandong
wangyulong
xiaqichao@ict.ac.cn