cmd "make dtb" can create dtb file: Bonito3a3000_7a.dtb, and link with gzrom.bin to create gzrom-dtb.bin
rename Targets/LS2K/conf/ls2k.dts to Targets/LS2K/conf/LS2K.dts
Change-Id: I8ba7dcd6b0e8cc875324666d5774cfd8fa9a10f6
Target: Bonito3a84w
1. add debug HT RX signals in loongson3_HT_init.S (disabled)
2. change clock frequency to 800/533
3. change the DDR3 params and pass the memory test
4. fix the conf files (AUTO_DDR_CONFIG not supported yet)
5. fix the command files about kernel parameters
6. fix the i2c read by GPIO
Change-Id: I6ceba17f5f149e16615caec2fb9e0726d2840b3e
1.Support uart, gmac on 2G, PS2, usb-ohci,
Sata, Vga, rtc and Pci net card devices.
2.The function of gmac on 2G needs modification
about PCB board.
3.The function of Sata needs modification
about Sata clock chip.
4.The series of 2G1A board include:
2G3+1A+DDR2, 2G5+1A+DDR2, 2G5+1A+DDR3.
The last one, PS2 is on 2G, the others are on 1A.
5.Modify Targets/Bonito2g1a/conf/Bonito.2g1a
Modify Targets/Bonito2g5ddr2_1a/conf/Bonito.2g5ddr2_1a
Modify pmon/dev/kbd.c and pmon/dev/kbd.h because of
the PS2 difference.
Target: LS2G5 + 1A + DDR3
Change-Id: I66f1e78e5672dd706331746c64c4db45371dfc00
1.Add zloader.2g5ddr2_1a and Target/Bonito2g5ddr2
2.Port the new MC initialization code for 2j5.(ARB_LEVEL cannot pass compiling now).
3.Modify the start.S for the difference between 2g3 and 2g5:
* The jr instructions can only use the ra register
* Hardware initialise scache
* Shut down the store fill buffer for scache coherent
Change-Id: I7d2946ea02ed95763688202d750e9644bae14807
Target:2G5+1A+DDR2
1:add Targets / Bonito2g1a director
2:add zloader .2 g1a director
3:add LOONGSON2G1A configure option
4:add start_2g1a.S and modify some config window
5:fixup some problem to support 2 g1a in start_2g1a.S
6:disable some funtions, then the pmon can run on command line
Change-Id: I19ee7a6d90c7efda3d6e986d12903da20ccc6ad5
Target:LS2G1A
1.Add Targets/Bonito2g5536 directory
2.Add zloader.2g5536 directory
3.Add Makefile.2g5536 file
4.Add usb and ps2 keyboard functions
5.Modify 2g5536 codes to support gcc4.4
6.Modify gmac code in sys/dev/gmac for net device
Change-Id: I73c343fb4b08a50cb515cd7cbefaf624b6065498
Target:2G5536
Now ls3c2h platform support added, SPI flash/AHCI sata/Gmac/LPC/DC
are all OK, however there are still some work to do:
1.The command "ifaddr eth0" can't work, but "ifaddr syn0" works;
2.It hasn't been test with Dimms on con5 and con7;
3.CPU Frequency aren't calculated by RTC, it's fixed by program.
4.It cost ls3c a long time to wait Vide Ram intilized by ls2h, the
time should be shrunken largely.
Target: Bonito3c2h
Oirginal script file use "mipsel-linux-objdump" to dump "pmon",
but the command maybe not available on all machines for most case,
which leads failure to resolve important symbals such as "_edata"
and "_end", so "objdump" is used instread of "mipsel-linux-objdump".
Now compile error is disappeared, and "gzram" can be used to debug
pmon code in C environment, this will save time in ddr, cache and
scache initialization.
Target: all
1, This version currently supports the processor core, UART, I2C bus, DDR2 controller,
GMAC controller, NAND controller, interrupt controller, the LPC controller, SPI controller,
HDA controller, the RTC, Watchdog, the HT interface.
2, This version does not support media processors, GPU, Display Controller, SATA controller,
USB 2.0 controller, ACPI power management, PCIE interface.
3, If you want to fall back to the previous version, please use the following command:
"git clone http://10.2.5.28/gitweb/pmon-loongson3a+2h", then git reset to the place you want to reach.
Original code missed support for ls3b server board, Now the code
is added, and passed test with ls3bserver board v1.1, it can boot
2Gx4 NUMA kernle with 4 short KVR 2G DDR3 dimms.
Target:Bonito3bserver
Make softlink Bonito3b780e/pci to Bonito3a780e/pci.
For this, 3A and 3B can use the same pci configure.
Signed-off-by: mengxiaofu <mengxiaofu@ict.ac.cn>
large video frame buffer up to 512M for bridge chip connected with HT bus.
It PASS test only in GUP_SP mode, which is the defalut mode in 3A780e branch of PMON.
Address space between 0x40000000 and 0x7fffffff is map to 1G memory space before, now
system momery size is at leaset 2G, so the space is left free to be used as PCI MEM space.
While PCI IO Space and HT Space is the same as before.
NOTICE: pci mem space base address need to be changed to 0x40000000 in kenrel source code
if this patch is applied, otherwise kernel will boot fail. If the bridge chip is connected
to PCIX controler in Loongson CPU, this patch should be changed to be applied.
Target: Bontio3a780e
QiaoChong
yangzhongkai
zhangbaoqi
xuwenrui
mengtianfang
Huang Pei
lixuefeng
Chen Xinke
Chenming
xiaqichao@ict.ac.cn
meiwenbin
shshzhang
xuhaoyu
sizhiying
wanghongmei
LI Wengang
CAI Wanwei
LIU Qi