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183 lines
3.7 KiB
183 lines
3.7 KiB
#ifndef _KERNEL
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#define _KERNEL
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#endif
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#define zero $0 /* always zero */
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#define AT $at /* assembler temp */
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#define v0 $2 /* return value */
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#define v1 $3
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#define a0 $4 /* argument registers */
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#define a1 $5
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#define a2 $6
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#define a3 $7
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#define t0 $8 /* temp registers (not saved across subroutine calls) */
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#define t1 $9
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#define t2 $10
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#define t3 $11
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#define t4 $12
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#define t5 $13
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#define t6 $14
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#define t7 $15
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#define s0 $16 /* saved across subroutine calls (callee saved) */
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#define s1 $17
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#define s2 $18
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#define s3 $19
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#define s4 $20
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#define s5 $21
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#define s6 $22
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#define s7 $23
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#define t8 $24 /* two more temp registers */
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#define t9 $25
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#define k0 $26 /* kernel temporary */
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#define k1 $27
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#define gp $28 /* global pointer */
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#define sp $29 /* stack pointer */
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#define s8 $30 /* one more callee saved */
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#define ra $31 /* return address */
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/*
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* Coprocessor 0 registers:
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*/
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#define COP_0_TLB_INDEX $0
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#define COP_0_TLB_RANDOM $1
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#define COP_0_TLB_LO0 $2
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#define COP_0_TLB_LO1 $3
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#define COP_0_TLB_CONTEXT $4
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#define COP_0_TLB_PG_MASK $5
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#define COP_0_TLB_WIRED $6
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#define COP_0_BAD_VADDR $8
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#define COP_0_COUNT $9
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#define COP_0_TLB_HI $10
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#define COP_0_COMPARE $11
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#define COP_0_STATUS_REG $12
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#define COP_0_CAUSE_REG $13
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#define COP_0_EXC_PC $14
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#define COP_0_PRID $15
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#define COP_0_CONFIG $16
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#define COP_0_LLADDR $17
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#define COP_0_WATCH_LO $18
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#define COP_0_WATCH_HI $19
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#define COP_0_TLB_XCONTEXT $20
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#define COP_0_ECC $26
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#define COP_0_CACHE_ERR $27
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#define COP_0_TAG_LO $28
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#define COP_0_TAG_HI $29
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#define COP_0_ERROR_PC $30
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/* RM7000 specific */
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#define COP_0_WATCH_1 $18
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#define COP_0_WATCH_2 $19
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#define COP_0_WATCH_M $24
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#define COP_0_PC_COUNT $25
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#define COP_0_PC_CTRL $22
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#define COP_0_ICR $20 /* CFC */
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#define COP_0_DERR_0 $26 /* CFC */
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#define COP_0_DERR_1 $27 /* CFC */
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#define SR_BOOT_EXC_VEC 0x00400000
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//---------------------------------------------------
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#define CONFIG_CACHE_64K_4WAY 1
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#define tmpsize s1
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#define msize s2
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#define sdShape s3
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#define bonito s4
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#define dbg s5
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#define sdCfg s6
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#define CFG_IB 0x00000020
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#define CFG_DB 0x00000010
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#define CFG_C_WBACK 3
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#define CFG_BE 0x00008000
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#define CFG_EPMASK 0x0f000000
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#define CFG_EPD 0x00000000
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#define CFG_EM_R4K 0x00000000
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#define CFG_EMMASK 0x00c00000
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#define CFG_AD 0x00800000
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#define CP0_CONFIG $16
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#define CP0_TAGLO $28
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#define CP0_TAGHI $29
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#define DDR100 0x04041091
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#define DDR266 0x0410435e
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#define DDR300 0x041453df
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/*
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* Register usage:
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*
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* s0 link versus load offset, used to relocate absolute adresses.
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* s1 free
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* s2 memory size.
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* s3 sdShape.
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* s4 Bonito base address.
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* s5 dbg.
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* s6 sdCfg.
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* s7 rasave.
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* s8 L3 Cache size.
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*/
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.set noreorder
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.globl _start
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.globl start
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.globl __main
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_start:
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start:
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.globl stack
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stack = start - 0x4000 /* Place PMON stack below PMON start in RAM */
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mtc0 zero, COP_0_STATUS_REG
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mtc0 zero, COP_0_CAUSE_REG
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li t0, SR_BOOT_EXC_VEC /* Exception to Boostrap Location */
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mtc0 t0, COP_0_STATUS_REG
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la sp, stack
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la gp, _gp
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move s1,a3 //struct callvectors *cv
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bal locate /* Get current execute address */
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nop
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/*
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* We get here from executing a bal to get the PC value of the current execute
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* location into ra. Check to see if we run from ROM or if this is ramloaded.
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*/
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locate:
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la s0,start
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subu s0,ra,s0
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and s0,0xffff0000
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#if 1 //ʹ��cache
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mfc0 a0,COP_0_CONFIG
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and a0,a0,0xfffffff8
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or a0,a0,0x3
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mtc0 a0,COP_0_CONFIG
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#endif
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/* Clear BSS */
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la a0, _edata
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la a2, _end
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2: sw zero, 0(a0)
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bne a2, a0, 2b
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addu a0, 4
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li a0, 0
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sw a0, CpuTertiaryCacheSize /* Set L3 cache size */
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li a0,MEMSIZE
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move a1,s1
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la v0, initmips
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jalr v0
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nop
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stuck:
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b stuck
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nop
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.rdata
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hexchar:
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.ascii "0123456789abcdef"
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.text
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.align 2
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