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243 lines
7.6 KiB
243 lines
7.6 KiB
/*
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* p6032/sbd.h: Algorithmics P-6032 board definition header file
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*
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* Copyright (c) 2000 Algorithmics Ltd - all rights reserved.
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*
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* This program is NOT free software, it is supplied under the terms
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* of the SDE-MIPS License Agreement, a copy of which is available at:
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*
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* http://www.algor.co.uk/algor/info/sde-license.pdf
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*
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* Any company which has obtained and signed a valid SDE-MIPS license
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* may use and modify this software internally and use (without
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* restrictions) any derived binary. You may not, however,
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* redistribute this in whole or in part as source code, nor may you
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* modify or remove any part of this copyright message.
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*/
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#ifndef __SBD_H__
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#define __SBD_H__
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#ifndef MHZ
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/* fastest possible pipeline clock */
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#define MHZ 200
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#endif
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#ifndef SYSCLK_MHZ
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/* fastest possible bus clock */
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#define SYSCLK_MHZ 100
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#endif
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#define RAMCYCLE 60 /* ~60ns dram cycle */
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#define ROMCYCLE 800 /* ~1500ns rom cycle */
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#define CACHECYCLE (1000/MHZ) /* pipeline clock */
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#define CYCLETIME CACHECYCLE
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#define CACHEMISS (CYCLETIME * 6)
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/*
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* rough scaling factors for 2 instruction DELAY loop to get 1ms and 1us delays
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*/
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#define ASMDELAY(ns,icycle) \
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(((ns) + (icycle)) / ((icycle) * 2))
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#define CACHENS(ns) ASMDELAY((ns), CACHECYCLE)
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#define RAMNS(ns) ASMDELAY((ns), CACHEMISS+RAMCYCLE)
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#define ROMNS(ns) ASMDELAY((ns), CACHEMISS+ROMCYCLE)
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#define CACHEUS(us) ASMDELAY((us)*1000, CACHECYCLE)
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#define RAMUS(us) ASMDELAY((us)*1000, CACHEMISS+RAMCYCLE)
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#define ROMUS(us) ASMDELAY((us)*1000, CACHEMISS+ROMCYCLE)
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#define CACHEMS(ms) ((ms) * ASMDELAY(1000000, CACHECYCLE))
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#define RAMMS(ms) ((ms) * ASMDELAY(1000000, CACHEMISS+RAMCYCLE))
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#define ROMMS(ms) ((ms) * ASMDELAY(1000000, CACHEMISS+ROMCYCLE))
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#ifndef __ASSEMBLER__
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extern void _sbd_nsdelay (unsigned long);
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#define nsdelay(ns) _sbd_nsdelay(ns)
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#define usdelay(us) _sbd_nsdelay((us)*1000)
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#define msdelay(ms) _sbd_nsdelay((ms)*1000000)
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#endif
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#define PCI_MEM_SPACE (BONITO_PCILO_BASE+0x00000000) /* 192MB */
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#define PCI_MEM_SPACE_SIZE BONITO_PCILO_SIZE
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#define PCI_IO_SPACE BONITO_PCIIO_BASE /* 1MB */
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#define PCI_IO_SPACE_SIZE BONITO_PCIIO_SIZE
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#define PCI_CFG_SPACE BONITO_PCICFG_BASE /* 512KB */
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#define PCI_CFG_SPACE_SIZE BONITO_PCICFG_SIZE
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#define BOOTPROM_BASE BONITO_BOOT_BASE
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#define BONITO_BASE BONITO_REG_BASE
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#define CPLD_BASE (BONITO_DEV_BASE+0x00000) /* IOCS0 */
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#define LED_BASE (BONITO_DEV_BASE+0x40000) /* IOCS1 */
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#define IDE0_BASE (BONITO_DEV_BASE+0x80000) /* IOCS2 */
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#define IDE1_BASE (BONITO_DEV_BASE+0xc0000) /* IOCS3 */
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#define FLASH_BASE BONITO_FLASH_BASE
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#define FLASH_SIZE BONITO_FLASH_SIZE
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#define BOOT_BASE BONITO_BOOT_BASE
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#define BOOT_SIZE BONITO_BOOT_SIZE
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#define SOCKET_BASE BONITO_SOCKET_BASE
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#define SOCKET_SIZE BONITO_SOCKET_SIZE
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#define PCI_IDSEL_SLOT1 13
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#define PCI_IDSEL_SLOT2 14
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#define PCI_IDSEL_SLOT3 15
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#define PCI_IDSEL_SLOT4 16
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#define PCI_IDSEL_I82371 17
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#define PCI_IDSEL_ETH 13 //qiaochong
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#define PCI_IDSEL_BONITO 19
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/* Define UART baud rate and register layout */
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#define NS16550_HZ (24000000/13)
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#ifdef __ASSEMBLER__
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#if #endian(big)
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#define NSREG(x) ((x)^3)
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#else
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#define NSREG(x) (x)
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#endif
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#else
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#define nsreg(x) unsigned char x
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#if #endian(big)
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#define nslayout(r0,r1,r2,r3) nsreg(r3); nsreg(r2); nsreg(r1); nsreg(r0)
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#endif
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#endif
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#define UART0_BASE ISAPORT_BASE(UART0_PORT)
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#define UART1_BASE ISAPORT_BASE(UART1_PORT)
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/* Bonito GPIO definitions */
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#define PIO_PCI_IRQA BONITO_GPIO_IOR(0) /* PCI IRQA */
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#define PIO_PCI_IRQB BONITO_GPIO_IOR(1) /* PCI IRQB */
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#define PIO_PCI_IRQC BONITO_GPIO_IOR(2) /* PCI IRQC */
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#define PIO_PCI_IRQD BONITO_GPIO_IOR(3) /* PCI IRQD */
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#define PIO_CPLDARB BONITO_GPIO_IOW(4) /* CPLD arbiter */
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#define PIO_PCIRESET BONITO_GPIO_IOW(5) /* PCI reset */
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#define PIO_ISA_NMI BONITO_GPIO_IN(0) /* ISA NMI */
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#define PIO_ISA_IRQ BONITO_GPIO_IN(1) /* ISA IRQ */
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#define PIO_ETH_IRQ BONITO_GPIO_IN(2) /* Ethernet IRQ */
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#define PIO_IDE_IRQ BONITO_GPIO_IN(3) /* Bonito IDE IRQ */
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#define PIO_UART1_IRQ BONITO_GPIO_IN(4) /* ISA IRQ3 */
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#define PIO_UART0_IRQ BONITO_GPIO_IN(5) /* ISA IRQ4 */
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/* ICU masks */
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#define ICU_PCI_IRQA BONITO_ICU_GPIO(0)
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#define ICU_PCI_IRQB BONITO_ICU_GPIO(1)
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#define ICU_PCI_IRQC BONITO_ICU_GPIO(2)
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#define ICU_PCI_IRQD BONITO_ICU_GPIO(3)
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#define ICU_NMI_IRQ BONITO_ICU_GPIN(0)
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#define ICU_ISA_IRQ BONITO_ICU_GPIN(1)
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#define ICU_ETH_IRQ BONITO_ICU_GPIN(2)
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#define ICU_BIDE_IRQ BONITO_ICU_GPIN(3)
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#define ICU_UART1_IRQ BONITO_ICU_GPIN(4)
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#define ICU_UART0_IRQ BONITO_ICU_GPIN(5)
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#define ICU_DRAMPERR BONITO_ICU_DRAMPERR
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#define ICU_CPUPERR BONITO_ICU_CPUPERR
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#define ICU_IDEDMA BONITO_ICU_IDEDMA
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#define ICU_PCICOPIER BONITO_ICU_PCICOPIER
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#define ICU_POSTEDRD BONITO_ICU_POSTEDRD
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#define ICU_PCIIRQ BONITO_ICU_PCIIRQ
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#define ICU_MASTERERR BONITO_ICU_MASTERERR
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#define ICU_SYSTEMERR BONITO_ICU_SYSTEMERR
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#define ICU_RETRYERR BONITO_ICU_RETRYERR
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#define ICU_MBOXES BONITO_ICU_MBOXES
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/* default PIO input enable */
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#define PIO_IE (~(PIO_CPLDARB|PIO_PCIRESET))
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/* ISA addresses */
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#define ISAPORT_BASE(x) (PCI_IO_SPACE + (x))
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#define ISAMEM_BASE(x) (PCI_MEM_SPACE + (x))
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/* ISA i/o ports */
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#define DMA1_PORT 0x000
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#define ICU1_PORT 0x020
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#define CTC_PORT 0x040
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#define DIAG_PORT 0x061
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#define RTC_ADDR_PORT 0x070
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#define RTC_DATA_PORT 0x071
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#define KEYBD_PORT 0x060
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#define DMAPAGE_PORT 0x080
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#define SYSC_PORT 0x092
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#define ICU2_PORT 0x0a0
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#define DMA2_PORT 0x0c0
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#define IDE_PORT 0x1f0
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#define UART1_PORT 0x2f8
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#define UART0_PORT 0x3f8
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#define ECP_PORT 0x378
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#define CEN_LATCH_PORT 0x37c /* P5064 special */
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#define FDC_PORT 0x3f0
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#define PM_PORT 0x3f80 //0x8000 //,[15:6]
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#define SMB_PORT 0x3fc0 //0x7000 //[15:4],/* Intel convention? */
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#define IDE_PORT_FIX1 0x3f50 //0xff10
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#define IDE_PORT_FIX2 0x3f60 //0xff80
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#define GPO_REG (0x34+PM_PORT)
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#define UART1_485 (1<<17)
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#define UART1_422 (1<<18)
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#define UART2_485 (1<<19)
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#define UART2_422 (1<<20)
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#define UART1_232 (1<<21)
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#define UART2_232 (1<<0)
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#define LAN1_EN (1<<8)
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#define LAN2A_EN (1<<27)
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#define LAN2B_EN (1<<28)
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#define GPIO_SETS ((1<<15)|(1<<16))
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/* ISA interrupt numbers */
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#define TIMER0_IRQ 0
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#define KEYBOARD_IRQ 1
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#define ICU2_IRQ 2
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#define SERIAL2_IRQ 3
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#define SERIAL1_IRQ 4
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#define PARALLEL2_IRQ 5
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#define FDC_IRQ 6
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#define PARALLEL1_IRQ 7
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#define RTC_IRQ 8
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#define NET_IRQ 9
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#define MATH_IRQ 13
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#define IDE_IRQ 14
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#define _SBD_FLASHENV 0 /* Store environment in flash #0 */
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#undef _SBD_RTCENV /* Store environment in RTC */
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#define RTC_HZ 16
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#define RTC_RATE RTC_RATE_16Hz
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#ifndef __ASSEMBLER__
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/* prototypes for board specific functions */
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#if defined(FLASHDEV_OK)
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extern flashcookie_t _sbd_bflashopen (paddr_t);
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extern flashcookie_t _sbd_uflashopen (paddr_t);
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#endif
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/* urgh - find some other way to prototype these functions FIXME */
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#if defined(__FLASHROM_H__)
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extern int _flash8_probe (struct fromcookie *fcp, unsigned int o);
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extern int _flash16_probe (struct fromcookie *fcp, unsigned int o);
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#endif
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#if !defined(PMON)
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extern void _bonito_iobc_wbinv (unsigned int pa, size_t nb);
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extern void _bonito_iobc_inval (unsigned int pa, size_t nb);
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extern void _bonito_clean_dcache (void *va, size_t nb);
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extern void _bonito_inval_dcache (void *va, size_t nb);
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#endif
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#endif
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#if !defined(__ASSEMBLER__) && !defined(inb)
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/* i/o port access ala 80x86 for ISA bus peripherals */
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unsigned char inb (unsigned int);
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unsigned short inw (unsigned int);
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unsigned long inl (unsigned int);
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void outb (unsigned int, unsigned char);
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void outw (unsigned int, unsigned short);
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void outl (unsigned int, unsigned long);
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void * ioport_map (unsigned int);
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#endif
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/* divert device drivers to Bonito-specific cache cleaning code */
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#define _sbd_clean_dcache _bonito_clean_dcache
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#define _sbd_inval_dcache _bonito_inval_dcache
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#endif /* __SBD_H__ */
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