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86 lines
2.7 KiB
86 lines
2.7 KiB
#include "rs780.h"
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/*****************************************
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* Compliant with CIM_33's ATINB_MiscClockCtrl
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*****************************************/
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void static rs780_config_misc_clk(device_t nb_dev)
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{
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u32 reg;
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u16 word;
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/* u8 byte; */
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//struct bus pbus; /* fake bus for dev0 fun1 */
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reg = pci_read_config32(nb_dev, 0x4c);
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reg |= 1 << 0;
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pci_write_config32(nb_dev, 0x4c, reg);
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word = pci_read_config16(_pci_make_tag(0, 0, 1), 0xf8);
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word &= 0xf00;
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pci_write_config16(_pci_make_tag(0, 0, 1), 0xf8, word);
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word = pci_read_config16(_pci_make_tag(0, 0, 1), 0xe8);
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word &= ~((1 << 12) | (1 << 13) | (1 << 14));
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word |= 1 << 13;
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pci_write_config16(_pci_make_tag(0, 0, 1), 0xe8, word);
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reg = pci_read_config32(_pci_make_tag(0, 0, 1), 0x94);
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reg &= ~((1 << 16) | (1 << 24) | (1 << 28));
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pci_write_config32(_pci_make_tag(0, 0, 1), 0x94, reg);
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reg = pci_read_config32(_pci_make_tag(0, 0, 1), 0x8c);
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reg &= ~((1 << 13) | (1 << 14) | (1 << 24) | (1 << 25));
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reg |= 1 << 13;
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pci_write_config32(_pci_make_tag(0, 0, 1), 0x8c, reg);
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reg = pci_read_config32(_pci_make_tag(0, 0, 1), 0xcc);
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reg |= 1 << 24;
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pci_write_config32(_pci_make_tag(0, 0, 1), 0xcc, reg);
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reg = nbmc_read_index(nb_dev, 0x7a);
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reg &= ~0x3f;
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reg |= 1 << 2;
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reg &= ~(1 << 6);
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set_htiu_enable_bits(nb_dev, 0x05, 1 << 11, 1 << 11);
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nbmc_write_index(nb_dev, 0x7a, reg);
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/* Powering Down efuse and strap block clocks after boot-up. GFX Mode. */
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reg = pci_read_config32(_pci_make_tag(0, 0, 1), 0xcc);
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reg &= ~(1 << 23);
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reg |= 1 << 24;
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pci_write_config32(_pci_make_tag(0, 0, 1), 0xcc, reg);
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/* BTDC: Programming NB CLK table. */
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{
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u8 temp8;
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//temp8 = pci_cf8_conf1.read8(&pbus, 0, 1, 0xe0);
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temp8 = pci_read_config8(_pci_make_tag(0, 0, 1), 0xe0);
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temp8 |= 0x01;
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//pci_cf8_conf1.write8(&pbus, 0, 1, 0xe0, temp8);
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pci_write_config8(_pci_make_tag(0, 0, 1), 0xe0, temp8);
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}
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#if 0
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/* Powerdown reference clock to graphics core PLL in northbridge only mode */
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reg = pci_read_config32(_pci_make_tag(0, 0, 1), 0x8c);
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reg |= 1 << 21;
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pci_write_config32(_pci_make_tag(0, 0, 1), 0x8c, reg);
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/* Powering Down efuse and strap block clocks after boot-up. NB Only Mode. */
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reg = pci_read_config32(_pci_make_tag(0, 0, 1), 0xcc);
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reg |= (1 << 23) | (1 << 24);
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pci_write_config32(_pci_make_tag(0, 0, 1), 0xcc, reg);
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/* Powerdown clock to memory controller in northbridge only mode */
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byte = pci_read_config8(_pci_make_tag(0, 0, 1), 0xe4);
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byte |= 1 << 0;
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pci_write_config8(_pci_make_tag(0,0, 1), 0xe4, reg);
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/* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */
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/* TODO: */
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#endif
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reg = pci_read_config32(nb_dev, 0x4c);
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reg &= ~(1 << 0);
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pci_write_config32(nb_dev, 0x4c, reg);
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set_htiu_enable_bits(nb_dev, 0x05, 7 << 8, 7 << 8);
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}
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