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88 lines
2.6 KiB
88 lines
2.6 KiB
#include "sb700.h"
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#include "rs780_cmn.h"
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#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
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#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
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#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
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#define DMA2_MODE_REG 0xD6 /* mode register (w) */
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#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
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#define INB(addr) (*(volatile unsigned char *) (addr))
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#define INW(addr) (*(volatile unsigned short *) (addr))
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#define INL(addr) (*(volatile unsigned int *) (addr))
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#define OUTB(b,addr) (*(volatile unsigned char *) (addr) = (b))
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#define OUTW(b,addr) (*(volatile unsigned short *) (addr) = (b))
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#define OUTL(b,addr) (*(volatile unsigned int *) (addr) = (b))
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static void isa_dma_init(void)
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{
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/* slave at 0x00 - 0x0f */
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/* master at 0xc0 - 0xdf */
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/* 0x80 - 0x8f DMA page registers */
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/* DMA: 0x00, 0x02, 0x4, 0x06 base address for DMA channel */
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OUTB(0, DMA1_RESET_REG);
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OUTB(0, DMA2_RESET_REG);
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OUTB(DMA_MODE_CASCADE, DMA2_MODE_REG);
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OUTB(0, DMA2_MASK_REG);
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}
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static void lpc_init(device_t dev)
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{
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u8 byte;
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u32 dword;
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device_t sm_dev;
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/* Enable the LPC Controller */
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printk_info("Enable the LPC Controller\n");
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//sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
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sm_dev = _pci_make_tag(0, 0x14, 0);
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dword = pci_read_config32(sm_dev, 0x64);
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dword |= 1 << 20;
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pci_write_config32(sm_dev, 0x64, dword);
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/* Initialize isa dma */
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//printk_info("Initialize isa dma\n");
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//isa_dma_init();
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/* RPR 7.2 Enable DMA transaction on the LPC bus */
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printk_info("Enable DMA transaction on the LPC bus\n");
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byte = pci_read_config8(dev, 0x40);
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byte |= (1 << 2);
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pci_write_config8(dev, 0x40, byte);
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/* RPR 7.3 Disable the timeout mechanism on LPC */
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printk_info("Disable the timeout mechanism on LPC\n");
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byte = pci_read_config8(dev, 0x48);
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byte &= ~(1 << 7);
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pci_write_config8(dev, 0x48, byte);
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/* RPR 7.5 Disable LPC MSI Capability */
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printk_info("Disable LPC MSI Capability\n");
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byte = pci_read_config8(dev, 0x78);
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byte &= ~(1 << 1);
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pci_write_config8(dev, 0x78, byte);
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#if 0
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//add by lycheng
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printk_info("IO/Mem Decoding\n");
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byte = pci_read_config8(dev, 0xbb);
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byte |= ((1<<3)|(1<<6)|(1<<7));
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pci_write_config8(dev, 0xbb, byte);
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/* Set a default latency timer. */
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pci_write_config8(dev, 0x0d, 0x40); //PCI_LATENCY_TIMER
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byte = pci_read_config8(dev, 0x3d); //PCI_INTERRUPT_PIN
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if (byte) {
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pci_write_config8(dev, 0x3c, 0); //PCI_INTERRUPT_LINE
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}
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/* Set the cache line size, so far 64 bytes is good for everyone. */
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pci_write_config8(dev, 0x0c, 64 >> 2); //PCI_CACHE_LINE_SIZE
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#endif
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}
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