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417 lines
12 KiB
417 lines
12 KiB
/* $Id: if_gt.h,v 1.1.1.1 2006/09/14 01:59:08 root Exp $ */
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/*
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* Copyright (c) 2001 Allegro Networks (www.allegronetworks.com)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Allegro Networks Inc.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#ifndef _GTETH_H
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#define _GTETH_H
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#include <target/pmon_target.h>
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#define ADDRESS_TABLE_ALIGNMENT 0x8
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#define MAC_ENTRY_SIZE 8
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#define MAC_ADDRESS_STRING_SIZE 12
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#define _8K_TABLE 0
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#define HASH_DEFUALT_MODE 14
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#define HASH_MODE 13
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#define HASH_SIZE 12
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#define PROMISCUOUS_MODE 0
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#define _8K_TABLE 0
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#define VALID 1
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#define SKIP 1<<1
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#define SKIP_BIT 1
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#define HOP_NUMBER 12
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#define EIGHT_K 0x8000
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#define HALF_K 0x8000/16
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#define MAX_NUMBER_OF_ADDRESSES_TO_STORE 1000
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#define NIBBLE_SWAPPING_16_BIT(X) (((X&0xf)<<4) | ((X&0xf0)>>4) | ((X&0xf00)<<4) | ((X&0xf000)>>4))
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#define NIBBLE_SWAPPING_32_BIT(X) (((X&0xf)<<4) | ((X&0xf0)>>4) | ((X&0xf00)<<4) | ((X&0xf000)>>4) | ((X&0xf0000)<<4) | ((X&0xf00000)>>4) | ((X&0xf000000)<<4) | ((X&0xf0000000)>>4))
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#define GT_NIBBLE(X) ((X&0x1)<<3)+((X&0x2)<<1)+((X&0x4)>>1)+((X&0x8)>>3)
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#define FLIP_6_BITS(X) (((X&0x1)<<5)+((X&0x2)<<3)+((X&0x4)<<1)+((X&0x8)>>1)+((X&0x10)>>3)+((X&0x20)>>5))
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#define FLIP_9_BITS(X) (((X&0x1)<<8)+((X&0x2)<<6)+((X&0x4)<<4)+((X&0x8)<<2)+((X&0x10)<<0)+((X&0x20)>>2)+((X&0x40)>>4)+((X&0x80)>>6)+((X&0x100)>>8))
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typedef struct AddressTablestore
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{
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unsigned int macL;
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unsigned int macH:16;
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unsigned int rd:1;
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unsigned int skip:1;
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unsigned int valid:1;
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} ADDRESS_TABLE_STORE;
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int hashTableFunction __P((u_int, u_int, int, int));
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int initAddressTable __P((int, int, int, int));
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int addAddressTableEntry __P((int, u_int, u_int, u_int, u_int));
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boolean_t enableFiltering __P((int));
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boolean_t disableFiltering __P((int port));
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boolean_t scanAddressTable __P((int port));
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boolean_t findFirstAddressTableEntry __P((int, u_int *,char *));
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boolean_t addressTableDefragment __P((int, int, int, int));
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boolean_t addressTableClear __P((int));
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/* Keep the ring sizes a power of two for efficiency. */
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#define TX_RING_SIZE 8
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#define TX_BUF_SZ 1536 /* Size of each temporary Tx buffer.*/
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#define RX_RING_SIZE 8
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#define RX_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
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#define RX_HASH_TABLE_SIZE 16384
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#define HASH_HOP_NUMBER 12
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#define ETH_IO_SIZE 0x400
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#define GTETH_READ(sc, off) \
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GT_READ((sc->port_offset + off))
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#define GTETH_WRITE(sc, off, data) \
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GT_WRITE((sc->port_offset + off), data)
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#define GTETH_SETBIT(sc, off, bits) {\
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u_int32_t val = GTETH_READ(sc, off) | (u_int32_t)(bits); \
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GTETH_WRITE(sc, off, val); }
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#define GTETH_CLRBIT(sc, off, bits) {\
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u_int32_t val = GTETH_READ(sc, off) & (u_int32_t)(~(bits); \
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GTETH_WRITE(sc, off, val); }
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/* Bit definitions of the SMI Reg */
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enum {
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SMIR_DATAMASK = 0xffff,
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SMIR_PHYADMASK = 0x1f<<16,
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SMIR_PHYADBIT = 16,
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SMIR_REGADMASK = 0x1f<<21,
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SMIR_REGADBIT = 21,
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SMIR_READOP = 1<<26,
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SMIR_READVALID = 1<<27,
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SMIR_BUSY = 1<<28
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};
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/* Bit definitions of the Port Config Reg */
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enum pcr_bits {
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pcrPM = 1,
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pcrRBM = 2,
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pcrPBF = 4,
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pcrEN = 1<<7,
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pcrLPBKMask = 0x3<<8,
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pcrLPBKBit = 8,
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pcrFC = 1<<10,
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pcrHS = 1<<12,
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pcrHM = 1<<13,
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pcrHDM = 1<<14,
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pcrHD = 1<<15,
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pcrISLMask = 0x7<<28,
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pcrISLBit = 28,
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pcrACCS = 1<<31
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};
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/* Bit definitions of the Port Config Extend Reg */
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enum pcxr_bits {
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pcxrIGMP = 1,
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pcxrSPAN = 2,
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pcxrPAR = 4,
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pcxrPRIOtxMask = 0x7<<3,
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pcxrPRIOtxBit = 3,
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pcxrPRIOrxMask = 0x3<<6,
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pcxrPRIOrxBit = 6,
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pcxrPRIOrxOverride = 1<<8,
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pcxrDPLXen = 1<<9,
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pcxrFCTLen = 1<<10,
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pcxrFLP = 1<<11,
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pcxrFCTL = 1<<12,
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pcxrMFLMask = 0x3<<14,
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pcxrMFLBit = 14,
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pcxrMIBclrMode = 1<<16,
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pcxrSpeed = 1<<18,
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pcxrSpeeden = 1<<19,
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pcxrRMIIen = 1<<20,
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pcxrDSCPen = 1<<21
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};
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/* Bit definitions of the Port Command Reg */
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enum pcmr_bits {
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pcmrFJ = 1<<15
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};
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/* Bit definitions of the Port Status Reg */
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enum psr_bits {
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psrSpeed = 1,
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psrDuplex = 2,
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psrFctl = 4,
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psrLink = 8,
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psrPause = 1<<4,
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psrTxLow = 1<<5,
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psrTxHigh = 1<<6,
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psrTxInProg = 1<<7
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};
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/* Bit definitions of the SDMA Config Reg */
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enum sdcr_bits {
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sdcrRCMask = 0xf<<2,
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sdcrRCBit = 2,
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sdcrBLMR = 1<<6,
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sdcrBLMT = 1<<7,
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sdcrPOVR = 1<<8,
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sdcrRIFB = 1<<9,
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sdcrBSZMask = 0x3<<12,
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sdcrBSZBit = 12
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};
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/* Bit definitions of the SDMA Command Reg */
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enum sdcmr_bits {
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sdcmrERD = 1<<7,
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sdcmrAR = 1<<15,
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sdcmrSTDH = 1<<16,
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sdcmrSTDL = 1<<17,
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sdcmrTXDH = 1<<23,
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sdcmrTXDL = 1<<24,
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sdcmrAT = 1<<31
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};
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/* Bit definitions of the Interrupt Cause Reg */
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enum icr_bits {
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icrRxBuffer = 1,
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icrTxBufferHigh = 1<<2,
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icrTxBufferLow = 1<<3,
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icrTxEndHigh = 1<<6,
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icrTxEndLow = 1<<7,
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icrRxError = 1<<8,
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icrTxErrorHigh = 1<<10,
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icrTxErrorLow = 1<<11,
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icrRxOVR = 1<<12,
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icrTxUdr = 1<<13,
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icrRxBufferQ0 = 1<<16,
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icrRxBufferQ1 = 1<<17,
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icrRxBufferQ2 = 1<<18,
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icrRxBufferQ3 = 1<<19,
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icrRxErrorQ0 = 1<<20,
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icrRxErrorQ1 = 1<<21,
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icrRxErrorQ2 = 1<<22,
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icrRxErrorQ3 = 1<<23,
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icrMIIPhySTC = 1<<28,
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icrSMIdone = 1<<29,
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icrEtherIntSum = 1<<31
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};
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/*
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* The Rx and Tx descriptor lists. (funny swapping rules...)
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*/
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#if BYTE_ORDER == LITTLE_ENDIAN
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typedef struct {
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u_int32_t cmdstat;
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u_int32_t byte_cnt_res;
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u_int32_t buff_ptr;
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u_int32_t next;
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} TX_DESC;
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typedef struct {
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u_int32_t cmdstat;
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u_int32_t byte_sz_cnt;
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u_int32_t buff_ptr;
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u_int32_t next;
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} RX_DESC;
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#else
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typedef struct {
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u_int32_t byte_cnt_res;
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u_int32_t cmdstat;
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u_int32_t next;
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u_int32_t buff_ptr;
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} TX_DESC;
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typedef struct {
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u_int32_t byte_sz_cnt;
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u_int32_t cmdstat;
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u_int32_t next;
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u_int32_t buff_ptr;
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} RX_DESC;
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#endif
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/* Values for the Tx command-status descriptor entry. */
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enum td_cmdstat {
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txOwn = 1<<31,
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txAutoMode = 1<<30,
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txEI = 1<<23,
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txGenCRC = 1<<22,
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txPad = 1<<18,
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txFirst = 1<<17,
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txLast = 1<<16,
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txErrorSummary = 1<<15,
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txReTxCntMask = 0x0f<<10,
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txReTxCntBit = 10,
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txCollision = 1<<9,
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txReTxLimit = 1<<8,
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txUnderrun = 1<<6,
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txLateCollision = 1<<5
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};
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#define TxReTxCntBit 10
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/* Values for the Rx command-status descriptor entry. */
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enum rd_cmdstat {
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rxOwn = 1<<31,
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rxAutoMode = 1<<30,
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rxEI = 1<<23,
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rxFirst = 1<<17,
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rxLast = 1<<16,
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rxErrorSummary = 1<<15,
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rxIGMP = 1<<14,
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rxHashExpired = 1<<13,
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rxMissedFrame = 1<<12,
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rxFrameType = 1<<11,
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rxShortFrame = 1<<8,
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rxMaxFrameLen = 1<<7,
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rxOverrun = 1<<6,
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rxCollision = 1<<4,
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rxCRCError = 1
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};
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/* Bit fields of a Hash Table Entry */
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enum hash_table_entry {
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hteValid = 1,
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hteSkip = 2,
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hteRD = 4
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};
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// The GT64240 MIB counters
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typedef struct {
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u_int32_t bytesReceived;
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u_int32_t bytesSent;
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u_int32_t framesReceived;
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u_int32_t framesSent;
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u_int32_t totalBytesReceived;
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u_int32_t totalFramesReceived;
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u_int32_t broadcastFramesReceived;
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u_int32_t multicastFramesReceived;
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u_int32_t CRCErrors;
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u_int32_t oversizeFrames;
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u_int32_t fragments;
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u_int32_t jabber;
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u_int32_t collisions;
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u_int32_t lateCollisions;
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u_int32_t frames64_bytes;
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u_int32_t frames65_127_bytes;
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u_int32_t frames128_255_bytes;
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u_int32_t frames256_511_bytes;
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u_int32_t frames512_1023_bytes;
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u_int32_t frames1024_MaxSize;
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u_int32_t rxErrors;
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u_int32_t droppedFrames;
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u_int32_t multicastFramesSent;
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u_int32_t broadcastFramesSent;
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u_int32_t undersizeFrames;
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} mib_counters_t;
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/*
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* Network device statistics. Akin to the 2.0 ether stats but
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* with byte counters.
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*/
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struct net_device_stats
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{
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unsigned long rx_packets; /* total packets received */
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unsigned long tx_packets; /* total packets transmitted */
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unsigned long rx_bytes; /* total bytes received */
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unsigned long tx_bytes; /* total bytes transmitted */
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unsigned long rx_errors; /* bad packets received */
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unsigned long tx_errors; /* packet transmit problems */
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unsigned long rx_dropped; /* no space in linux buffers */
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unsigned long tx_dropped; /* no space available in linux */
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unsigned long multicast; /* multicast packets received */
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unsigned long collisions;
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/* detailed rx_errors: */
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unsigned long rx_length_errors;
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unsigned long rx_over_errors; /* receiver ring buff overflow */
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unsigned long rx_crc_errors; /* recved pkt with crc error */
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unsigned long rx_frame_errors; /* recv'd frame alignment error */
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unsigned long rx_fifo_errors; /* recv'r fifo overrun */
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unsigned long rx_missed_errors; /* receiver missed packet */
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/* detailed tx_errors */
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unsigned long tx_aborted_errors;
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unsigned long tx_carrier_errors;
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unsigned long tx_fifo_errors;
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unsigned long tx_heartbeat_errors;
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unsigned long tx_window_errors;
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/* for cslip etc */
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unsigned long rx_compressed;
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unsigned long tx_compressed;
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};
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struct gt_softc {
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struct device sc_dev; /* Generic device structures */
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void *sc_ih; /* Interrupt handler cookie */
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bus_space_tag_t sc_st; /* Bus space tag */
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bus_space_handle_t sc_sh; /* Bus space handle */
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pci_chipset_tag_t sc_pc; /* Chipset handle needed by mips */
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struct arpcom arpcom; /* Per interface network data */
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RX_DESC* rx_ring;
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TX_DESC* tx_ring;
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u_int32_t* rx_hash;
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int hash_mode;
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/*
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* Tx buffers with less than 8 bytes
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* of payload must be 8-byte aligned
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*/
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char* tx_bp;
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int rx_next_out; /* The next free ring entry to receive */
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int tx_next_in; /* The next free ring entry to send */
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int tx_next_out; /* The last ring entry the ISR processed */
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int tx_count; /* Number of packets waiting to be sent in Tx ring */
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int tx_queued;
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int tx_full; /* Tx ring is full */
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struct mbuf **rx_m; /* Receive buffer mbuf linkage */
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struct mbuf **tx_m; /* Transmit buffer mbuf linkage */
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mib_counters_t mib;
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struct net_device_stats stats;
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int chip_rev;
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u_int32_t port_offset;
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int phy_addr; /* PHY address */
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unsigned char phys[2]; /* MII device addresses */
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};
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#endif
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