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519 lines
19 KiB
519 lines
19 KiB
/*
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* Bonito Register Map
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* Copyright (c) 1999 Algorithmics Ltd
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*
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* Algorithmics gives permission for anyone to use and modify this file
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* without any obligation or license condition except that you retain
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* this copyright message in any source redistribution in whole or part.
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*
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* Updated copies of this and other files can be found at
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* ftp://ftp.algor.co.uk/pub/bonito/
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*
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* Users of the Bonito controller are warmly recommended to contribute
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* any useful changes back to Algorithmics (mail to
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* bonito@algor.co.uk).
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*/
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/* Revision 1.48 autogenerated on 08/17/99 15:20:01 */
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#ifndef _BONITO_H_
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#ifdef __ASSEMBLER__
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//__ASSEMBLER__ is not defined
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/* offsets from base register */
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#define BONITO(x) (x)
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#else /* !__ASSEMBLER */
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extern char *heaptop;
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/* offsets from base pointer, this construct allows optimisation */
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/* static char * const _bonito = PA_TO_KVA1(BONITO_BASE); */
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/*#define BONITO(x) *(volatile unsigned long *)(PHYS_TO_UNCACHED(BONITO_REG_BASE)+(x))*/
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#define BONITO(x) *(volatile unsigned long *)(0xbfe00000+(x))
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#endif /* __ASSEMBLER__ */
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#define RTC_INDEX_REG 0x70
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#define RTC_DATA_REG 0x71
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#define RTC_NVRAM_BASE 0x0e
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#define GS3_UART0_BASE 0xbfe001e0
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#define GS3_UART1_BASE 0xbfe001e8
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#define GS3_UART_BASE GS3_UART0_BASE
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#ifdef LS3_HT
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#define COM1_BASE_ADDR 0xb80003f8
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#define COM2_BASE_ADDR 0xb80002f8
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#else
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#define COM1_BASE_ADDR 0xbfd003f8
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#define COM2_BASE_ADDR 0xbfd002f8
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#endif
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#ifndef COM3_BASE_ADDR
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#define COM3_BASE_ADDR 0xbff003f8
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#endif
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//#define NS16550HZ 1843200
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#define NS16550HZ 3686400
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/*********************************************************************/
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/*nvram define */
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/*********************************************************************/
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#ifdef NVRAM_IN_FLASH
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# define NVRAM_SIZE 494
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# define NVRAM_SECSIZE 500
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# define NVRAM_OFFS 0x000fd800
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# define ETHER_OFFS 494 /* Ethernet address base */
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#else /* Use clock ram, 256 bytes only */
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# define NVRAM_SIZE 114
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# define NVRAM_SECSIZE NVRAM_SIZE /* Helper */
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# define NVRAM_OFFS 0
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# define ETHER_OFFS 108 /* Ethernet address base */
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#endif
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/*********************************************************************/
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/*PCI map */
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/*********************************************************************/
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#ifdef X86_LIKE_SPACE
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/* To make address spaces alike with x86 system, we put sdram
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* start address at 0 and pci devices' start address at 0x14000000 for
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* both CPU address space & PCI memory address space.
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*
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* We have 3 64M window in CPU address space to access PCI memory,but the
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* legacy PCI start pci memory from 0x10000000, so we can use the same address to access
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* them from cpu memory space. But to access the 0xc0000 vga ram, we have to
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* reserve the first window. Only the last two are used for pci devices.
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* --zfx 060716
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*/
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/* make sdram appear at both cpu & pci memory space 0,
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* so for dma the physical address can be directly used
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* as bus address. --zfx 060716
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*/
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#define PCI_MEM_SPACE_PCI_BASE 0x40000000
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#define PCI_LOCAL_MEM_PCI_BASE 0x00000000
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#define PCI_LOCAL_MEM_ISA_BASE 0x80000000
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#define PCI_LOCAL_REG_PCI_BASE 0x90000000
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#else
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#define PCI_MEM_SPACE_PCI_BASE 0x40000000
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#define PCI_LOCAL_MEM_PCI_BASE 0x80000000
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#define PCI_LOCAL_MEM_ISA_BASE 0x00800000
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#define PCI_LOCAL_REG_PCI_BASE 0x90000000
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#endif
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#define PCI_IO_SPACE_BASE 0x00000000
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#define BONITO_BOOT_BASE 0x1fc00000
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#define BONITO_BOOT_SIZE 0x00100000
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#define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1)
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#define BONITO_FLASH_BASE 0x1fc00000
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#define BONITO_FLASH_SIZE 0x03000000
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#define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1)
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#define BONITO_SOCKET_BASE 0x1f800000
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#define BONITO_SOCKET_SIZE 0x00400000
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#define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1)
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#define BONITO_REG_BASE 0x1fe00000
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#define BONITO_REG_SIZE 0x00040000
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#define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1)
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#define BONITO_DEV_BASE 0x1ff00000
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#define BONITO_DEV_SIZE 0x00100000
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#define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1)
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#define BONITO_PCILO_BASE 0x40000000
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#define BONITO_PCILO_BASE_VA 0xc0000000
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#ifdef LS3_HT
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#define BONITO_PCILO_SIZE 0x40000000
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#else
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#define BONITO_PCILO_SIZE 0x0c000000
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#endif
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#define BONITO_PCILO_TOP (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1)
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#define BONITO_PCILO0_BASE 0x40000000
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#define BONITO_PCILO1_BASE 0x80000000
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#ifdef LS3_HT
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//#define BONITO_PCILO2_BASE 0x1c000000
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//#define BONITO_PCIHI_BASE 0x18000000
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//#define BONITO_PCIHI_SIZE 0x02000000
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//#define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1)
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//#define BONITO_PCIIO_BASE 0x1fd00000
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//#define BONITO_PCIIO_BASE_VA 0xbfd00000
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#define BONITO_PCIIO_BASE 0x18000000
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#define BONITO_PCIIO_BASE_VA 0xb8000000
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#define BONITO_PCIIO_SIZE 0x02000000
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#else
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#define BONITO_PCILO2_BASE 0x18000000
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#define BONITO_PCIHI_BASE 0x20000000
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#define BONITO_PCIHI_SIZE 0x20000000
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#define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1)
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#define BONITO_PCIIO_BASE 0x1fd00000
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#define BONITO_PCIIO_BASE_VA 0xbfd00000
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#define BONITO_PCIIO_SIZE 0x00010000
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#endif
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#define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1)
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#define BONITO_PCICFG_BASE 0x1a000000
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#define BONITO_PCICFG_SIZE 0x00080000
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#define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1)
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#define BONITO_PCICFG0_BASE 0x1a000000
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#define BONITO_PCICFG1_BASE 0x1b000000
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#define BONITO_PCICFG0_BASE_VA 0xba000000
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#define BONITO_PCICFG1_BASE_VA 0xbb000000
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/* Bonito Register Bases */
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#define BONITO_PCICONFIGBASE 0x00
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#define BONITO_REGBASE 0x100
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/* PCI Configuration Registers */
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#define BONITO_PCI_REG(x) BONITO(BONITO_PCICONFIGBASE + (x))
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#define BONITO_PCIDID BONITO_PCI_REG(0x00)
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#define BONITO_PCICMD BONITO_PCI_REG(0x04)
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#define BONITO_PCICLASS BONITO_PCI_REG(0x08)
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#define BONITO_PCILTIMER BONITO_PCI_REG(0x0c)
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#define BONITO_PCIBASE0 BONITO_PCI_REG(0x10)
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#define BONITO_PCIBASE1 BONITO_PCI_REG(0x14)
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#define BONITO_PCIBASE2 BONITO_PCI_REG(0x18)
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#define BONITO_PCIEXPRBASE BONITO_PCI_REG(0x30)
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#define BONITO_PCIINT BONITO_PCI_REG(0x3c)
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#define BONITO_PCICMD_PERR_CLR 0x80000000
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#define BONITO_PCICMD_SERR_CLR 0x40000000
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#define BONITO_PCICMD_MABORT_CLR 0x20000000
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#define BONITO_PCICMD_MTABORT_CLR 0x10000000
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#define BONITO_PCICMD_TABORT_CLR 0x08000000
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#define BONITO_PCICMD_MPERR_CLR 0x01000000
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#define BONITO_PCICMD_PERRRESPEN 0x00000040
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#define BONITO_PCICMD_ASTEPEN 0x00000080
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#define BONITO_PCICMD_SERREN 0x00000100
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#define BONITO_PCILTIMER_BUSLATENCY 0x0000ff00
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#define BONITO_PCILTIMER_BUSLATENCY_SHIFT 8
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/* 1. Bonito h/w Configuration */
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/* Power on register */
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#define BONITO_BONPONCFG BONITO(BONITO_REGBASE + 0x00)
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#define BONITO_BONPONCFG_SYSCONTROLLERRD 0x00040000
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#define BONITO_BONPONCFG_ROMCS1SAMP 0x00020000
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#define BONITO_BONPONCFG_ROMCS0SAMP 0x00010000
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#define BONITO_BONPONCFG_CPUBIGEND 0x00004000
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#define BONITO_BONPONCFG_CPUPARITY 0x00002000
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#define BONITO_BONPONCFG_CPUTYPE 0x00000007
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#define BONITO_BONPONCFG_CPUTYPE_SHIFT 0
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#define BONITO_BONPONCFG_PCIRESET_OUT 0x00000008
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#define BONITO_BONPONCFG_IS_ARBITER 0x00000010
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#define BONITO_BONPONCFG_ROMBOOT 0x000000c0
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#define BONITO_BONPONCFG_ROMBOOT_SHIFT 6
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#define BONITO_BONPONCFG_ROMBOOT_FLASH (0x0<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
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#define BONITO_BONPONCFG_ROMBOOT_SOCKET (0x1<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
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#define BONITO_BONPONCFG_ROMBOOT_SDRAM (0x2<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
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#define BONITO_BONPONCFG_ROMBOOT_CPURESET (0x3<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
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#define BONITO_BONPONCFG_ROMCS0WIDTH 0x00000100
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#define BONITO_BONPONCFG_ROMCS1WIDTH 0x00000200
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#define BONITO_BONPONCFG_ROMCS0FAST 0x00000400
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#define BONITO_BONPONCFG_ROMCS1FAST 0x00000800
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#define BONITO_BONPONCFG_CONFIG_DIS 0x00000020
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/* Other Bonito configuration */
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#define BONITO_BONGENCFG_OFFSET 0x4
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#define BONITO_BONGENCFG BONITO(BONITO_REGBASE + BONITO_BONGENCFG_OFFSET)
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#define BONITO_BONGENCFG_DEBUGMODE 0x00000001
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#define BONITO_BONGENCFG_SNOOPEN 0x00000002
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#define BONITO_BONGENCFG_CPUSELFRESET 0x00000004
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#define BONITO_BONGENCFG_FORCE_IRQA 0x00000008
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#define BONITO_BONGENCFG_IRQA_ISOUT 0x00000010
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#define BONITO_BONGENCFG_IRQA_FROM_INT1 0x00000020
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#define BONITO_BONGENCFG_BYTESWAP 0x00000040
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#define BONITO_BONGENCFG_PREFETCHEN 0x00000100
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#define BONITO_BONGENCFG_WBEHINDEN 0x00000200
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#define BONITO_BONGENCFG_CACHEALG 0x00000c00
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#define BONITO_BONGENCFG_CACHEALG_SHIFT 10
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#define BONITO_BONGENCFG_PCIQUEUE 0x00001000
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#define BONITO_BONGENCFG_CACHESTOP 0x00002000
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#define BONITO_BONGENCFG_MSTRBYTESWAP 0x00004000
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#define BONITO_BONGENCFG_BUSERREN 0x00008000
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#define BONITO_BONGENCFG_NORETRYTIMEOUT 0x00010000
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#define BONITO_BONGENCFG_SHORTCOPYTIMEOUT 0x00020000
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/* 2. IO & IDE configuration */
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#define BONITO_IODEVCFG BONITO(BONITO_REGBASE + 0x08)
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/* 3. IO & IDE configuration */
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#define BONITO_SDCFG BONITO(BONITO_REGBASE + 0x0c)
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/* 4. PCI address map control */
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#define BONITO_PCIMAP BONITO(BONITO_REGBASE + 0x10)
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#define BONITO_PCIMEMBASECFG BONITO(BONITO_REGBASE + 0x14)
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#define BONITO_PCIMAP_CFG BONITO(BONITO_REGBASE + 0x18)
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/* 5. ICU & GPIO regs */
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/* GPIO Regs - r/w */
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#define BONITO_GPIODATA_OFFSET 0x1c
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#define BONITO_GPIODATA BONITO(BONITO_REGBASE + BONITO_GPIODATA_OFFSET)
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#define BONITO_GPIOIE BONITO(BONITO_REGBASE + 0x20)
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/* ICU Configuration Regs - r/w */
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#define BONITO_INTEDGE BONITO(BONITO_REGBASE + 0x24)
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#define BONITO_INTSTEER BONITO(BONITO_REGBASE + 0x28)
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#define BONITO_INTPOL BONITO(BONITO_REGBASE + 0x2c)
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/* ICU Enable Regs - IntEn & IntISR are r/o. */
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#define BONITO_INTENSET BONITO(BONITO_REGBASE + 0x30)
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#define BONITO_INTENCLR BONITO(BONITO_REGBASE + 0x34)
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#define BONITO_INTEN BONITO(BONITO_REGBASE + 0x38)
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#define BONITO_INTISR BONITO(BONITO_REGBASE + 0x3c)
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/* PCI mail boxes */
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#define BONITO_PCIMAIL0_OFFSET 0x40
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#define BONITO_PCIMAIL1_OFFSET 0x44
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#define BONITO_PCIMAIL2_OFFSET 0x48
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#define BONITO_PCIMAIL3_OFFSET 0x4c
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#define BONITO_PCIMAIL0 BONITO(BONITO_REGBASE + 0x40)
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#define BONITO_PCIMAIL1 BONITO(BONITO_REGBASE + 0x44)
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#define BONITO_PCIMAIL2 BONITO(BONITO_REGBASE + 0x48)
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#define BONITO_PCIMAIL3 BONITO(BONITO_REGBASE + 0x4c)
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/* 6. PCI cache */
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#define BONITO_PCICACHECTRL BONITO(BONITO_REGBASE + 0x50)
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#define BONITO_PCICACHETAG BONITO(BONITO_REGBASE + 0x54)
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#define BONITO_PCIBADADDR BONITO(BONITO_REGBASE + 0x58)
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#define BONITO_PCIMSTAT BONITO(BONITO_REGBASE + 0x5c)
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/*
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#define BONITO_PCIRDPOST BONITO(BONITO_REGBASE + 0x60)
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#define BONITO_PCIDATA BONITO(BONITO_REGBASE + 0x64)
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*/
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/* 7. IDE DMA & Copier */
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#define BONITO_CONFIGBASE 0x000
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#define BONITO_BONITOBASE 0x100
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#define BONITO_LDMABASE 0x200
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#define BONITO_COPBASE 0x300
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#define BONITO_REG_BLOCKMASK 0x300
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#define BONITO_LDMACTRL BONITO(BONITO_LDMABASE + 0x0)
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#define BONITO_LDMASTAT BONITO(BONITO_LDMABASE + 0x0)
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#define BONITO_LDMAADDR BONITO(BONITO_LDMABASE + 0x4)
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#define BONITO_LDMAGO BONITO(BONITO_LDMABASE + 0x8)
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#define BONITO_LDMADATA BONITO(BONITO_LDMABASE + 0xc)
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#define BONITO_COPCTRL BONITO(BONITO_COPBASE + 0x0)
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#define BONITO_COPSTAT BONITO(BONITO_COPBASE + 0x0)
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#define BONITO_COPPADDR BONITO(BONITO_COPBASE + 0x4)
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#define BONITO_COPDADDR BONITO(BONITO_COPBASE + 0x8)
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#define BONITO_COPGO BONITO(BONITO_COPBASE + 0xc)
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/* ###### Bit Definitions for individual Registers #### */
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/* Gen DMA. */
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#define BONITO_IDECOPDADDR_DMA_DADDR 0x0ffffffc
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#define BONITO_IDECOPDADDR_DMA_DADDR_SHIFT 2
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#define BONITO_IDECOPPADDR_DMA_PADDR 0xfffffffc
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#define BONITO_IDECOPPADDR_DMA_PADDR_SHIFT 2
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#define BONITO_IDECOPGO_DMA_SIZE 0x0000fffe
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#define BONITO_IDECOPGO_DMA_SIZE_SHIFT 0
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#define BONITO_IDECOPGO_DMA_WRITE 0x00010000
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#define BONITO_IDECOPGO_DMAWCOUNT 0x000f0000
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#define BONITO_IDECOPGO_DMAWCOUNT_SHIFT 16
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#define BONITO_IDECOPCTRL_DMA_STARTBIT 0x80000000
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#define BONITO_IDECOPCTRL_DMA_RSTBIT 0x40000000
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/* DRAM - sdCfg */
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#define BONITO_SDCFG_AROWBITS 0x00000003
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#define BONITO_SDCFG_AROWBITS_SHIFT 0
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#define BONITO_SDCFG_ACOLBITS 0x0000000c
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#define BONITO_SDCFG_ACOLBITS_SHIFT 2
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#define BONITO_SDCFG_ABANKBIT 0x00000010
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#define BONITO_SDCFG_ASIDES 0x00000020
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#define BONITO_SDCFG_AABSENT 0x00000040
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#define BONITO_SDCFG_AWIDTH64 0x00000080
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#define BONITO_SDCFG_BROWBITS 0x00000300
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#define BONITO_SDCFG_BROWBITS_SHIFT 8
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#define BONITO_SDCFG_BCOLBITS 0x00000c00
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#define BONITO_SDCFG_BCOLBITS_SHIFT 10
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#define BONITO_SDCFG_BBANKBIT 0x00001000
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#define BONITO_SDCFG_BSIDES 0x00002000
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#define BONITO_SDCFG_BABSENT 0x00004000
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#define BONITO_SDCFG_BWIDTH64 0x00008000
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#define BONITO_SDCFG_EXTRDDATA 0x00010000
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#define BONITO_SDCFG_EXTRASCAS 0x00020000
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#define BONITO_SDCFG_EXTPRECH 0x00040000
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#define BONITO_SDCFG_EXTRASWIDTH 0x00180000
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#define BONITO_SDCFG_EXTRASWIDTH_SHIFT 19
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#define BONITO_SDCFG_DRAMRESET 0x00200000
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#define BONITO_SDCFG_DRAMEXTREGS 0x00400000
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#define BONITO_SDCFG_DRAMPARITY 0x00800000
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/* PCI Cache - pciCacheCtrl */
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#define BONITO_PCICACHECTRL_CACHECMD 0x00000007
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#define BONITO_PCICACHECTRL_CACHECMD_SHIFT 0
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#define BONITO_PCICACHECTRL_CACHECMDLINE 0x00000018
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#define BONITO_PCICACHECTRL_CACHECMDLINE_SHIFT 3
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#define BONITO_PCICACHECTRL_CMDEXEC 0x00000020
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#define BONITO_IODEVCFG_BUFFBIT_CS0 0x00000001
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#define BONITO_IODEVCFG_SPEEDBIT_CS0 0x00000002
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#define BONITO_IODEVCFG_MOREABITS_CS0 0x00000004
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#define BONITO_IODEVCFG_BUFFBIT_CS1 0x00000008
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#define BONITO_IODEVCFG_SPEEDBIT_CS1 0x00000010
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#define BONITO_IODEVCFG_MOREABITS_CS1 0x00000020
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#define BONITO_IODEVCFG_BUFFBIT_CS2 0x00000040
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#define BONITO_IODEVCFG_SPEEDBIT_CS2 0x00000080
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#define BONITO_IODEVCFG_MOREABITS_CS2 0x00000100
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#define BONITO_IODEVCFG_BUFFBIT_CS3 0x00000200
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#define BONITO_IODEVCFG_SPEEDBIT_CS3 0x00000400
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#define BONITO_IODEVCFG_MOREABITS_CS3 0x00000800
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#define BONITO_IODEVCFG_BUFFBIT_IDE 0x00001000
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#define BONITO_IODEVCFG_SPEEDBIT_IDE 0x00002000
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#define BONITO_IODEVCFG_WORDSWAPBIT_IDE 0x00004000
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#define BONITO_IODEVCFG_MODEBIT_IDE 0x00008000
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#define BONITO_IODEVCFG_DMAON_IDE 0x001f0000
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#define BONITO_IODEVCFG_DMAON_IDE_SHIFT 16
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#define BONITO_IODEVCFG_DMAOFF_IDE 0x01e00000
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#define BONITO_IODEVCFG_DMAOFF_IDE_SHIFT 21
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#define BONITO_IODEVCFG_EPROMSPLIT 0x02000000
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/* gpio */
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#define BONITO_GPIO_GPIOW 0x000003ff
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#define BONITO_GPIO_GPIOW_SHIFT 0
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#define BONITO_GPIO_GPIOR 0x01ff0000
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#define BONITO_GPIO_GPIOR_SHIFT 16
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#define BONITO_GPIO_GPINR 0xfe000000
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#define BONITO_GPIO_GPINR_SHIFT 25
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#define BONITO_GPIO_IOW(N) (1<<(BONITO_GPIO_GPIOW_SHIFT+(N)))
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#define BONITO_GPIO_IOR(N) (1<<(BONITO_GPIO_GPIOR_SHIFT+(N)))
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#define BONITO_GPIO_INR(N) (1<<(BONITO_GPIO_GPINR_SHIFT+(N)))
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/* ICU */
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#define BONITO_ICU_MBOXES 0x0000000f
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#define BONITO_ICU_MBOXES_SHIFT 0
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#define BONITO_ICU_DMARDY 0x00000010
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#define BONITO_ICU_DMAEMPTY 0x00000020
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#define BONITO_ICU_COPYRDY 0x00000040
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#define BONITO_ICU_COPYEMPTY 0x00000080
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#define BONITO_ICU_COPYERR 0x00000100
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#define BONITO_ICU_PCIIRQ 0x00000200
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#define BONITO_ICU_MASTERERR 0x00000400
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#define BONITO_ICU_SYSTEMERR 0x00000800
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#define BONITO_ICU_DRAMPERR 0x00001000
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#define BONITO_ICU_RETRYERR 0x00002000
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#define BONITO_ICU_GPIOS 0x01ff0000
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#define BONITO_ICU_GPIOS_SHIFT 16
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#define BONITO_ICU_GPINS 0x7e000000
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#define BONITO_ICU_GPINS_SHIFT 25
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#define BONITO_ICU_MBOX(N) (1<<(BONITO_ICU_MBOXES_SHIFT+(N)))
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#define BONITO_ICU_GPIO(N) (1<<(BONITO_ICU_GPIOS_SHIFT+(N)))
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#define BONITO_ICU_GPIN(N) (1<<(BONITO_ICU_GPINS_SHIFT+(N)))
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/* pcimap */
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#define BONITO_PCIMAP_PCIMAP_LO0 0x0000003f
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#define BONITO_PCIMAP_PCIMAP_LO0_SHIFT 0
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#define BONITO_PCIMAP_PCIMAP_LO1 0x00000fc0
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#define BONITO_PCIMAP_PCIMAP_LO1_SHIFT 6
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#define BONITO_PCIMAP_PCIMAP_LO2 0x0003f000
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#define BONITO_PCIMAP_PCIMAP_LO2_SHIFT 12
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#define BONITO_PCIMAP_PCIMAP_2 0x00040000
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#define BONITO_PCIMAP_WIN(WIN,ADDR) ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
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#define BONITO_PCIMAP_WINSIZE (1<<26)
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#define BONITO_PCIMAP_WINOFFSET(ADDR) ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1))
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#define BONITO_PCIMAP_WINBASE(ADDR) ((ADDR) << 26)
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/* pcimembaseCfg */
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#define BONITO_PCIMEMBASECFG_MASK 0xf0000000
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#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK 0x0000001f
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#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK_SHIFT 0
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#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS 0x000003e0
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#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS_SHIFT 5
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#define BONITO_PCIMEMBASECFG_MEMBASE0_CACHED 0x00000400
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#define BONITO_PCIMEMBASECFG_MEMBASE0_IO 0x00000800
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#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK 0x0001f000
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#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK_SHIFT 12
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#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS 0x003e0000
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#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS_SHIFT 17
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#define BONITO_PCIMEMBASECFG_MEMBASE1_CACHED 0x00400000
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#define BONITO_PCIMEMBASECFG_MEMBASE1_IO 0x00800000
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#define BONITO_PCIMEMBASECFG_ASHIFT 23
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#define BONITO_PCIMEMBASECFG_AMASK 0x007fffff
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#define BONITO_PCIMEMBASECFGSIZE(WIN,SIZE) (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)
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#define BONITO_PCIMEMBASECFGBASE(WIN,BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS)
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#define BONITO_PCIMEMBASECFG_SIZE(WIN,CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK)
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#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
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#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
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#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
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#define BONITO_PCITOPHYS(WIN,ADDR,CFG) ( \
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(((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG)))) | \
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(BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG)) \
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)
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/* PCICmd */
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#define BONITO_PCICMD_MEMEN 0x00000002
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#define BONITO_PCICMD_MSTREN 0x00000004
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/* DDR - sdCfg */
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#define BONITO_SDCFG_TRC_SHIFT 0
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#define BONITO_SDCFG_TRP_SHIFT 2
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#define BONITO_SDCFG_TWR_SHIFT 3
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#define BONITO_SDCFG_TCAS_SHIFT 4
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#define BONITO_SDCFG_TRAS_SHIFT 6
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#define BONITO_SDCFG_TRFC_SHIFT 7
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#define BONITO_SDCFG_TRCD_SHIFT 9
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#define BONITO_SDCFG_TREF_SHIFT 10
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#define BONITO_SDCFG_DDRTYPE_SHIFT 22
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#define BONITO_SDCFG_ISSEQ_SHIFT 26
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#define BONITO_SDCFG_DIMM_MOD_NUM_SHIFT 27
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#define VTSB_BUS 0
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#ifdef PCI_IDSEL_VIA686B
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#define VTSB_DEV PCI_IDSEL_VIA686B
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#else
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#define VTSB_DEV 17
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#endif
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#define VTSB_ISA_FUNC 0
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#define VTSB_IDE_FUNC 1
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#endif /* _BONITO_H_ */
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