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414 lines
14 KiB
414 lines
14 KiB
/* $Id: bus.h,v 1.1.1.1 2006/09/14 01:59:08 root Exp $ */
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/*
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* Copyright (c) 1997 Per Fogelstrom. All rights reserved.
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* Copyright (c) 1996 Niklas Hallqvist. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Per Fogelstrom.
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* This product includes software developed by Niklas Hallqvist.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MACHINE_BUS_H_
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#define _MACHINE_BUS_H_
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#include <machine/pio.h>
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#ifdef __STDC__
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#define CAT(a,b) a##b
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#define CAT3(a,b,c) a##b##c
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#else
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#define CAT(a,b) a/**/b
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#define CAT3(a,b,c) a/**/b/**/c
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#endif
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/*
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* Bus access types.
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*/
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typedef u_int32_t bus_addr_t;
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typedef u_int32_t bus_size_t;
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typedef u_int32_t bus_space_handle_t;
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typedef struct tgt_bus_space *bus_space_tag_t;
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struct tgt_bus_space {
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u_int32_t bus_base;
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u_int32_t bus_reverse; /* Reverse bus ops (dummy) */
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};
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/*
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* Access methods for bus resources
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*/
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#define bus_space_map(t, addr, size, cacheable, bshp) \
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((*(bshp) = (t)->bus_base | (addr)), 0)
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#define bus_space_unmap(t, bsh, size)
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#define bus_space_subregion(t, bsh, offset, size, nbshp) \
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((*(nbshp) = (bsh) + (offset)), 0)
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/* DUMMIES */
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#define letoh8(x) (x)
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#define htole8(x) (x)
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#define bus_space_read(n,m) \
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static __inline CAT3(u_int,m,_t) \
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CAT(bus_space_read_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
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bus_addr_t ba) \
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{ \
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if(bst->bus_reverse) \
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return CAT(letoh,m)(*(volatile CAT3(u_int,m,_t) *)(bsh + ba));\
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else \
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return *(volatile CAT3(u_int,m,_t) *)(bsh + ba); \
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}
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bus_space_read(1,8)
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bus_space_read(2,16)
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bus_space_read(4,32)
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#define bus_space_read_8 !!! bus_space_read_8 unimplemented !!!
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#define bus_space_read_multi(n, m) \
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static __inline void \
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CAT(bus_space_read_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
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bus_size_t ba, CAT3(u_int,m,_t) *buf, bus_size_t cnt) \
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{ \
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while (cnt--) \
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*buf++ = CAT(bus_space_read_,n)(bst, bsh, ba); \
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}
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bus_space_read_multi(1,8)
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bus_space_read_multi(2,16)
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bus_space_read_multi(4,32)
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#if 0
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#define bus_space_read_multi_1(t, h, o, a, c) do { \
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insb((u_int8_t *)((h) + (o)), (a), (c)); \
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} while(0)
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#define bus_space_read_multi_2(t, h, o, a, c) do { \
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insw((u_int16_t *)((h) + (o)), (a), (c)); \
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} while(0)
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#define bus_space_read_multi_4(t, h, o, a, c) do { \
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insl((u_int32_t *)((h) + (o)), (a), (c)); \
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} while(0)
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#endif
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#define bus_space_read_multi_8 !!! bus_space_read_multi_8 not implemented !!!
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#define bus_space_read_region(n,m) \
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static __inline void \
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CAT(bus_space_read_region_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
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bus_size_t ba, CAT3(u_int,m,_t) *x, size_t cnt) \
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{ \
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while (cnt--) { \
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*x++ = CAT(bus_space_read_,n)(bst, bsh, ba); \
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ba += sizeof(*x); \
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} \
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}
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bus_space_read_region(1,8)
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bus_space_read_region(2,16)
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bus_space_read_region(4,32)
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#define bus_space_read_region_8 !!! bus_space_read_region_8 not implemented !!!
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#define bus_space_write(n,m) \
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static __inline void \
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CAT(bus_space_write_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
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bus_addr_t ba, CAT3(u_int,m,_t) x) \
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{ \
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if(bst->bus_reverse) \
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*(volatile CAT3(u_int,m,_t) *)(bsh + ba) = CAT(htole,m)(x); \
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else \
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*(volatile CAT3(u_int,m,_t) *)(bsh + ba) = x; \
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}
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bus_space_write(1,8)
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bus_space_write(2,16)
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bus_space_write(4,32)
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#define bus_space_write_8 !!! bus_space_write_8 unimplemented !!!
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#define bus_space_write_multi(n, m) \
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static __inline void \
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CAT(bus_space_write_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
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bus_size_t ba, const CAT3(u_int,m,_t) *buf, bus_size_t cnt) \
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{ \
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while (cnt--) \
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CAT(bus_space_write_,n)(bst, bsh, ba, *buf++); \
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}
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bus_space_write_multi(1,8)
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bus_space_write_multi(2,16)
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bus_space_write_multi(4,32)
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#if 0
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#define bus_space_write_multi_1(t, h, o, a, c) do { \
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outsb((u_int8_t *)((h) + (o)), (a), (c)); \
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} while(0)
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#define bus_space_write_multi_2(t, h, o, a, c) do { \
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outsw((u_int16_t *)((h) + (o)), (a), (c)); \
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} while(0)
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#define bus_space_write_multi_4(t, h, o, a, c) do { \
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outsl((u_int32_t *)((h) + (o)), (a), (c)); \
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} while(0)
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#endif
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#define bus_space_write_multi_8 !!! bus_space_write_multi_8 not implemented !!!
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#define bus_space_write_region(n,m) \
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static __inline void \
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CAT(bus_space_write_region_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
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bus_size_t ba, const CAT3(u_int,m,_t) *x, size_t cnt) \
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{ \
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while (cnt--) { \
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CAT(bus_space_write_,n)(bst, bsh, ba, *x++); \
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ba += sizeof(*x); \
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} \
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}
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bus_space_write_region(1,8)
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bus_space_write_region(2,16)
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bus_space_write_region(4,32)
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#define bus_space_write_region_8 \
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!!! bus_space_write_region_8 not implemented !!!
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#define bus_space_set_region(n,m) \
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static __inline void \
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CAT(bus_space_set_region_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
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bus_addr_t ba, CAT3(u_int,m,_t) x, size_t cnt) \
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{ \
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while (cnt--) \
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CAT(bus_space_write_,n)(bst, bsh, ba++, x); \
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}
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bus_space_set_region(1,8)
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bus_space_set_region(2,16)
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bus_space_set_region(4,32)
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#define bus_space_write_8 !!! bus_space_write_8 unimplemented !!!
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/* These are OpenBSD extensions to the general NetBSD bus interface. */
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#define bus_space_read_raw_multi(n,m,l) \
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static __inline void \
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CAT(bus_space_read_raw_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
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bus_addr_t ba, u_int8_t *buf, bus_size_t cnt) \
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{ \
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CAT(bus_space_read_multi_,n)(bst, bsh, ba, (CAT3(u_int,m,_t) *)buf, \
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cnt >> l); \
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}
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bus_space_read_raw_multi(2,16,1)
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bus_space_read_raw_multi(4,32,2)
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#define bus_space_read_raw_multi_8 \
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!!! bus_space_read_raw_multi_8 not implemented !!!
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#define bus_space_write_raw_multi(n,m,l) \
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static __inline void \
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CAT(bus_space_write_raw_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh,\
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bus_addr_t ba, const u_int8_t *buf, bus_size_t cnt) \
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{ \
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CAT(bus_space_write_multi_,n)(bst, bsh, ba, \
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(const CAT3(u_int,m,_t) *)buf, cnt >> l); \
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}
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bus_space_write_raw_multi(2,16,1)
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bus_space_write_raw_multi(4,32,2)
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#define bus_space_write_raw_multi_8 \
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!!! bus_space_write_raw_multi_8 not implemented !!!
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/*
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* Bus read/write barrier methods
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* void bus_space_barrier(bus_space_tag_t tag,
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* bus_space_handle_t bsh, bus_size_t offset,
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* bus_size_t len, int flags);
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*/
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#define BUS_SPACE_BARRIER_WRITE 0x02 /* foece write barrier */
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#define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
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static inline void
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bus_space_barrier(bus_space_tag_t t, bus_space_handle_t h,
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bus_size_t o, bus_size_t l, int f)
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{
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__asm__ __volatile__ ("sync" ::: "memory");
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}
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#define bus_space_barrier(t, h, o, l, f) \
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((void)((void)(t), (void)(h), (void)(o), (void)(l),(void)(f)))
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#define BUS_DMA_WAITOK 0x00
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#define BUS_DMA_NOWAIT 0x01
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#define BUS_DMA_ALLOCNOW 0x02
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#define BUS_DMAMEM_NOSYNC 0x04
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#define BUS_DMA_COHERENT 0x04
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//wan+
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#define BUS_DMA_ZERO 0x800 /* zero memory in dmamem_alloc */
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/* Forwards needed by prototypes below. */
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struct mbuf;
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struct proc;
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struct uio;
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#define BUS_DMASYNC_POSTREAD 0x01
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#define BUS_DMASYNC_POSTWRITE 0x02
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#define BUS_DMASYNC_PREREAD 0x04
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#define BUS_DMASYNC_PREWRITE 0x08
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typedef int bus_dmasync_op_t;
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typedef struct tgt_bus_dma_tag *bus_dma_tag_t;
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typedef struct tgt_bus_dmamap *bus_dmamap_t;
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extern struct tgt_bus_dma_tag bus_dmamap_tag;
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/*
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* bus_dma_segment_t
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*
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* Describes a single contiguous DMA transaction. Values
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* are suitable for programming into DMA registers.
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*/
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struct tgt_bus_dma_segment {
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bus_addr_t ds_addr; /* DMA address */
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bus_size_t ds_len; /* length of transfer */
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vaddr_t ds_raddr; /* real buffer address */
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vaddr_t ds_daddr; /* dma buffer address */
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};
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typedef struct tgt_bus_dma_segment bus_dma_segment_t;
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/*
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* bus_dma_tag_t
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*
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* A machine-dependent opaque type describing the implementation of
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* DMA for a given bus.
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*/
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struct tgt_bus_dma_tag {
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void *_cookie; /* cookie used in the guts */
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/*
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* DMA mapping methods.
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*/
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int (*_dmamap_create) __P((void *, bus_size_t, int,
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bus_size_t, bus_size_t, int, bus_dmamap_t *));
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void (*_dmamap_destroy) __P((void *, bus_dmamap_t));
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int (*_dmamap_load) __P((void *, bus_dmamap_t, void *,
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bus_size_t, struct proc *, int));
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int (*_dmamap_load_mbuf) __P((void *, bus_dmamap_t,
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struct mbuf *, int));
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int (*_dmamap_load_uio) __P((void *, bus_dmamap_t,
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struct uio *, int));
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int (*_dmamap_load_raw) __P((void *, bus_dmamap_t,
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bus_dma_segment_t *, int, bus_size_t, int));
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void (*_dmamap_unload) __P((void *, bus_dmamap_t));
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void (*_dmamap_sync) __P((void *, bus_dmamap_t, bus_addr_t, bus_size_t, bus_dmasync_op_t));
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/*
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* DMA memory utility functions.
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*/
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int (*_dmamem_alloc) __P((void *, bus_size_t, bus_size_t,
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bus_size_t, bus_dma_segment_t *, int, int *, int));
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void (*_dmamem_free) __P((void *, bus_dma_segment_t *, int));
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int (*_dmamem_map) __P((void *, bus_dma_segment_t *,
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int, size_t, caddr_t *, int));
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void (*_dmamem_unmap) __P((void *, caddr_t, size_t));
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int (*_dmamem_mmap) __P((void *, bus_dma_segment_t *,
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int, int, int, int));
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bus_addr_t _dmamap_offs;
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};
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#define bus_dmamap_create(t, s, n, m, b, f, p) \
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(*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p))
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#define bus_dmamap_destroy(t, p) \
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(*(t)->_dmamap_destroy)((t), (p))
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#define bus_dmamap_load(t, m, b, s, p, f) \
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(*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f))
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#define bus_dmamap_load_mbuf(t, m, b, f) \
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(*(t)->_dmamap_load_mbuf)((t), (m), (b), (f))
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#define bus_dmamap_load_uio(t, m, u, f) \
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(*(t)->_dmamap_load_uio)((t), (m), (u), (f))
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#define bus_dmamap_load_raw(t, m, sg, n, s, f) \
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(*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f))
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#define bus_dmamap_unload(t, p) \
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(*(t)->_dmamap_unload)((t), (p))
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#define bus_dmamap_sync(t, p, o, l, h) \
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(void)((t)->_dmamap_sync ? \
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(*(t)->_dmamap_sync)((t), (p), (o), (l), (h)) : (void)0)
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#define bus_dmamem_alloc(t, s, a, b, sg, n, r, f) \
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(*(t)->_dmamem_alloc)((t)->_cookie, (s), (a), (b), (sg), (n), (r), (f))
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#define bus_dmamem_free(t, sg, n) \
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(*(t)->_dmamem_free)((t)->_cookie, (sg), (n))
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#define bus_dmamem_map(t, sg, n, s, k, f) \
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(*(t)->_dmamem_map)((t)->_cookie, (sg), (n), (s), (k), (f))
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#define bus_dmamem_unmap(t, k, s) \
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(*(t)->_dmamem_unmap)((t)->_cookie, (k), (s))
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#define bus_dmamem_mmap(t, sg, n, o, p, f) \
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(*(t)->_dmamem_mmap)((t)->_cookie, (sg), (n), (o), (p), (f))
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int _dmamap_create __P((void *, bus_size_t, int,
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bus_size_t, bus_size_t, int, bus_dmamap_t *));
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void _dmamap_destroy __P((void *, bus_dmamap_t));
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int _dmamap_load __P((void *, bus_dmamap_t, void *,
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bus_size_t, struct proc *, int));
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int _dmamap_load_mbuf __P((void *, bus_dmamap_t, struct mbuf *, int));
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int _dmamap_load_uio __P((void *, bus_dmamap_t, struct uio *, int));
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int _dmamap_load_raw __P((void *, bus_dmamap_t,
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bus_dma_segment_t *, int, bus_size_t, int));
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void _dmamap_unload __P((void *, bus_dmamap_t));
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void _dmamap_sync __P((void *, bus_dmamap_t, bus_addr_t, bus_size_t, bus_dmasync_op_t));
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int _dmamem_alloc __P((void *, bus_size_t, bus_size_t,
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bus_size_t, bus_dma_segment_t *, int, int *, int));
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void _dmamem_free __P((void *, bus_dma_segment_t *, int));
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int _dmamem_map __P((void *, bus_dma_segment_t *,
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int, size_t, caddr_t *, int));
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void _dmamem_unmap __P((void *, caddr_t, size_t));
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int _dmamem_mmap __P((void *, bus_dma_segment_t *, int, int, int, int));
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int dma_cachectl __P((caddr_t, int));
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/*
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* bus_dmamap_t
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*
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* Describes a DMA mapping.
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*/
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struct tgt_bus_dmamap {
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/*
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* PRIVATE MEMBERS: not for use by machine-independent code.
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*/
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bus_size_t _dm_size; /* largest DMA transfer mappable */
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int _dm_segcnt; /* number of segs this map can map */
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bus_size_t _dm_maxsegsz; /* largest possible segment */
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bus_size_t _dm_boundary; /* don't cross this */
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int _dm_flags; /* misc. flags */
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void *_dm_cookie; /* cookie for bus-specific functions */
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/*
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* PUBLIC MEMBERS: these are used by machine-independent code.
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*/
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bus_size_t dm_mapsize; /* size of the mapping */
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int dm_nsegs; /* # valid segments in mapping */
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bus_dma_segment_t dm_segs[1]; /* segments; variable length */
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};
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#endif /* _MACHINE_BUS_H_ */
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