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499 lines
16 KiB
499 lines
16 KiB
/* $OpenBSD: cpu.h,v 1.4 1998/09/15 10:50:12 pefo Exp $ */
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/*-
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Ralph Campbell and Rick Macklem.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Copyright (C) 1989 Digital Equipment Corporation.
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* Permission to use, copy, modify, and distribute this software and
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* its documentation for any purpose and without fee is hereby granted,
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* provided that the above copyright notice appears in all copies.
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* Digital Equipment Corporation makes no representations about the
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* suitability of this software for any purpose. It is provided "as is"
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* without express or implied warranty.
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*
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* from: @(#)cpu.h 8.4 (Berkeley) 1/4/94
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*/
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#ifndef _MIPS_CPU_H_
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#define _MIPS_CPU_H_
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#include <machine/psl.h>
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#define KUSEG_ADDR 0x0
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#define CACHED_MEMORY_ADDR 0x80000000
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#define UNCACHED_MEMORY_ADDR 0xa0000000
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#define KSEG2_ADDR 0xc0000000
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#define MAX_MEM_ADDR 0xbe000000
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#define RESERVED_ADDR 0xbfc80000
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#ifndef _LOCORE
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#define CACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff)
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#define PHYS_TO_CACHED(x) ((unsigned)(x) | CACHED_MEMORY_ADDR)
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#define UNCACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff)
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#define PHYS_TO_UNCACHED(x) ((unsigned)(x) | UNCACHED_MEMORY_ADDR)
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#define VA_TO_CINDEX(x) ((unsigned)(x) & 0xffffff | CACHED_MEMORY_ADDR)
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#define CACHED_TO_UNCACHED(x) (PHYS_TO_UNCACHED(CACHED_TO_PHYS(x)))
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#else
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#define CACHED_TO_PHYS(x) ((x) & 0x1fffffff)
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#define PHYS_TO_CACHED(x) ((x) | CACHED_MEMORY_ADDR)
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#define UNCACHED_TO_PHYS(x) ((x) & 0x1fffffff)
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#define PHYS_TO_UNCACHED(x) ((x) | UNCACHED_MEMORY_ADDR)
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#define VA_TO_CINDEX(x) ((x) & 0xffffff | CACHED_MEMORY_ADDR)
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#define CACHED_TO_UNCACHED(x) (PHYS_TO_UNCACHED(CACHED_TO_PHYS(x)))
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#endif
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#ifdef _KERNEL
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/*
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* The bits in the cause register.
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*
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* CR_BR_DELAY Exception happened in branch delay slot.
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* CR_COP_ERR Coprocessor error.
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* CR_IP Interrupt pending bits defined below.
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* CR_EXC_CODE The exception type (see exception codes below).
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*/
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#define CR_BR_DELAY 0x80000000
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#define CR_COP_ERR 0x30000000
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#define CR_EXC_CODE 0x0000007c
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#define CR_IP 0x0000FF00
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#define CR_EXC_CODE_SHIFT 2
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/*
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* The bits in the status register. All bits are active when set to 1.
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*/
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#define SR_COP_USABILITY 0xf0000000
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#define SR_COP_0_BIT 0x10000000
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#define SR_COP_1_BIT 0x20000000
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#define SR_RP 0x08000000
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#define SR_FR_32 0x04000000
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#define SR_RE 0x02000000
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#define SR_BOOT_EXC_VEC 0x00400000
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#define SR_TLB_SHUTDOWN 0x00200000
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#define SR_SOFT_RESET 0x00100000
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#define SR_DIAG_CH 0x00040000
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#define SR_DIAG_CE 0x00020000
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#define SR_DIAG_DE 0x00010000
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#define SR_KX 0x00000080
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#define SR_SX 0x00000040
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#define SR_UX 0x00000020
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#define SR_KSU_MASK 0x00000018
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#define SR_KSU_USER 0x00000010
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#define SR_KSU_SUPER 0x00000008
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#define SR_KSU_KERNEL 0x00000000
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#define SR_ERL 0x00000004
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#define SR_EXL 0x00000002
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#define SR_INT_ENAB 0x00000001
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/*#define SR_INT_MASK 0x0000ff00*/
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/*
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* The interrupt masks.
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* If a bit in the mask is 1 then the interrupt is enabled (or pending).
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*/
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#define INT_MASK 0xff00
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#define INT_MASK_5 0x8000
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#define INT_MASK_4 0x4000
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#define INT_MASK_3 0x2000
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#define INT_MASK_2 0x1000
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#define INT_MASK_1 0x0800
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#define INT_MASK_0 0x0400
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#define HARD_INT_MASK 0xfc00
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#define SOFT_INT_MASK_1 0x0200
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#define SOFT_INT_MASK_0 0x0100
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/*
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* RM7000 cause register expansion.
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*/
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#define INT_MASK_PERF 0x00200000 /* 13 Performance counter */
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#define INT_MASK_TIMR 0x00100000 /* 12 Timer */
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/*
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* The bits in the context register.
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*/
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#define CNTXT_PTE_BASE 0xff800000
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#define CNTXT_BAD_VPN2 0x007ffff0
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/*
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* Location of exception vectors.
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*/
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#define RESET_EXC_VEC 0xbfc00000
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#define TLB_MISS_EXC_VEC 0x80000000
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#define XTLB_MISS_EXC_VEC 0x80000080
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#define CACHE_ERR_EXC_VEC 0x80000100
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#define GEN_EXC_VEC 0x80000180
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/*
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* Coprocessor 0 registers:
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*/
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#define COP_0_TLB_INDEX $0
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#define COP_0_TLB_RANDOM $1
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#define COP_0_TLB_LO0 $2
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#define COP_0_TLB_LO1 $3
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#define COP_0_TLB_CONTEXT $4
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#define COP_0_TLB_PG_MASK $5
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#define COP_0_TLB_WIRED $6
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#define COP_0_BAD_VADDR $8
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#define COP_0_COUNT $9
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#define COP_0_TLB_HI $10
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#define COP_0_COMPARE $11
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#define COP_0_STATUS_REG $12
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#define COP_0_CAUSE_REG $13
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#define COP_0_EXC_PC $14
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#define COP_0_PRID $15
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#define COP_0_CONFIG $16
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#define COP_0_LLADDR $17
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#define COP_0_WATCH_LO $18
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#define COP_0_WATCH_HI $19
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#define COP_0_TLB_XCONTEXT $20
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#define COP_0_ECC $26
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#define COP_0_CACHE_ERR $27
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#define COP_0_TAG_LO $28
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#define COP_0_TAG_HI $29
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#define COP_0_ERROR_PC $30
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/* RM7000 specific */
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#define COP_0_WATCH_1 $18
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#define COP_0_WATCH_2 $19
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#define COP_0_WATCH_M $24
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#define COP_0_PC_COUNT $25
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#define COP_0_PC_CTRL $22
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#define COP_0_ICR $20 /* CFC */
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#define COP_0_DERR_0 $26 /* CFC */
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#define COP_0_DERR_1 $27 /* CFC */
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/*
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* Values for the code field in a break instruction.
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*/
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#define BREAK_INSTR 0x0000000d
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#define BREAK_VAL_MASK 0x03ff0000
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#define BREAK_VAL_SHIFT 16
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#define BREAK_KDB_VAL 512
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#define BREAK_SSTEP_VAL 513
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#define BREAK_BRKPT_VAL 514
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#define BREAK_SOVER_VAL 515
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#define BREAK_DDB_VAL 516
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#define BREAK_KDB (BREAK_INSTR | (BREAK_KDB_VAL << BREAK_VAL_SHIFT))
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#define BREAK_SSTEP (BREAK_INSTR | (BREAK_SSTEP_VAL << BREAK_VAL_SHIFT))
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#define BREAK_BRKPT (BREAK_INSTR | (BREAK_BRKPT_VAL << BREAK_VAL_SHIFT))
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#define BREAK_SOVER (BREAK_INSTR | (BREAK_SOVER_VAL << BREAK_VAL_SHIFT))
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#define BREAK_DDB (BREAK_INSTR | (BREAK_DDB_VAL << BREAK_VAL_SHIFT))
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/*
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* Mininum and maximum cache sizes.
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*/
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#define MIN_CACHE_SIZE (16 * 1024)
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#define MAX_CACHE_SIZE (256 * 1024)
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/*
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* The floating point version and status registers.
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*/
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#define FPC_ID $0
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#define FPC_CSR $31
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/*
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* The floating point coprocessor status register bits.
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*/
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#define FPC_ROUNDING_BITS 0x00000003
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#define FPC_ROUND_RN 0x00000000
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#define FPC_ROUND_RZ 0x00000001
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#define FPC_ROUND_RP 0x00000002
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#define FPC_ROUND_RM 0x00000003
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#define FPC_STICKY_BITS 0x0000007c
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#define FPC_STICKY_INEXACT 0x00000004
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#define FPC_STICKY_UNDERFLOW 0x00000008
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#define FPC_STICKY_OVERFLOW 0x00000010
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#define FPC_STICKY_DIV0 0x00000020
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#define FPC_STICKY_INVALID 0x00000040
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#define FPC_ENABLE_BITS 0x00000f80
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#define FPC_ENABLE_INEXACT 0x00000080
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#define FPC_ENABLE_UNDERFLOW 0x00000100
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#define FPC_ENABLE_OVERFLOW 0x00000200
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#define FPC_ENABLE_DIV0 0x00000400
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#define FPC_ENABLE_INVALID 0x00000800
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#define FPC_EXCEPTION_BITS 0x0003f000
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#define FPC_EXCEPTION_INEXACT 0x00001000
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#define FPC_EXCEPTION_UNDERFLOW 0x00002000
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#define FPC_EXCEPTION_OVERFLOW 0x00004000
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#define FPC_EXCEPTION_DIV0 0x00008000
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#define FPC_EXCEPTION_INVALID 0x00010000
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#define FPC_EXCEPTION_UNIMPL 0x00020000
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#define FPC_COND_BIT 0x00800000
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#define FPC_FLUSH_BIT 0x01000000
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#define FPC_MBZ_BITS 0xfe7c0000
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/*
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* Constants to determine if have a floating point instruction.
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*/
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#define OPCODE_SHIFT 26
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#define OPCODE_C1 0x11
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/*
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* The low part of the TLB entry.
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*/
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#define VMTLB_PF_NUM 0x3fffffc0
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#define VMTLB_ATTR_MASK 0x00000038
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#define VMTLB_MOD_BIT 0x00000004
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#define VMTLB_VALID_BIT 0x00000002
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#define VMTLB_GLOBAL_BIT 0x00000001
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#define VMTLB_PHYS_PAGE_SHIFT 6
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/*
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* The high part of the TLB entry.
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*/
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#define VMTLB_VIRT_PAGE_NUM 0xffffe000
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#define VMTLB_PID 0x000000ff
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#define VMTLB_PID_SHIFT 0
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#define VMTLB_VIRT_PAGE_SHIFT 12
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/*
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* The number of TLB entries and the first one that write random hits.
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*/
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/*#define VMNUM_TLB_ENTRIES 48 XXX We never use this... */
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#define VMWIRED_ENTRIES 8
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/*
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* The number of process id entries.
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*/
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#define VMNUM_PIDS 256
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/*
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* TLB probe return codes.
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*/
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#define VMTLB_NOT_FOUND 0
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#define VMTLB_FOUND 1
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#define VMTLB_FOUND_WITH_PATCH 2
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#define VMTLB_PROBE_ERROR 3
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/*
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* Exported definitions unique to mips cpu support.
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*/
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/*
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* definitions of cpu-dependent requirements
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* referenced in generic code
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*/
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#define COPY_SIGCODE /* copy sigcode above user stack in exec */
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#define cpu_wait(p) /* nothing */
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#define cpu_swapout(p) panic("cpu_swapout: can't get here");
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#ifndef _LOCORE
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/*
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* Arguments to hardclock and gatherstats encapsulate the previous
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* machine state in an opaque clockframe.
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*/
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struct clockframe {
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int pc; /* program counter at time of interrupt */
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int sr; /* status register at time of interrupt */
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int cr; /* cause register at time of interrupt */
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};
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#define CLKF_USERMODE(framep) ((framep)->sr & SR_KSU_USER)
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#define CLKF_BASEPRI(framep) ((~(framep)->sr & (INT_MASK|SR_INT_ENAB)) == 0)
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#define CLKF_PC(framep) ((framep)->pc)
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#define CLKF_INTR(framep) (0)
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/*
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* Preempt the current process if in interrupt from user mode,
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* or after the current trap/syscall if in system mode.
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*/
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#define need_resched() { want_resched = 1; aston(); }
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/*
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* Give a profiling tick to the current process when the user profiling
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* buffer pages are invalid. On the PICA, request an ast to send us
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* through trap, marking the proc as needing a profiling tick.
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*/
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#define need_proftick(p) { (p)->p_flag |= P_OWEUPC; aston(); }
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/*
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* Notify the current process (p) that it has a signal pending,
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* process as soon as possible.
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*/
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#define signotify(p) aston()
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#define aston() (astpending = 1)
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volatile int astpending; /* need to trap before returning to user mode */
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int want_resched; /* resched() was called */
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/*
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* CPU identification, from PRID register.
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*/
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union cpuprid {
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int cpuprid;
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struct {
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#if BYTE_ORDER == BIG_ENDIAN
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u_int pad1:16; /* reserved */
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u_int cp_imp:8; /* implementation identifier */
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u_int cp_majrev:4; /* major revision identifier */
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u_int cp_minrev:4; /* minor revision identifier */
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#else
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u_int cp_minrev:4; /* minor revision identifier */
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u_int cp_majrev:4; /* major revision identifier */
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u_int cp_imp:8; /* implementation identifier */
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u_int pad1:16; /* reserved */
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#endif
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} cpu;
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};
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/*
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* CTL_MACHDEP definitions.
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*/
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#define CPU_CONSDEV 1 /* dev_t: console terminal device */
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#define CPU_MAXID 2 /* number of valid machdep ids */
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#define CTL_MACHDEP_NAMES { \
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{ 0, 0 }, \
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{ "console_device", CTLTYPE_STRUCT }, \
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}
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#endif /* !_LOCORE */
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#endif /* _KERNEL */
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/*
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* MIPS CPU types (cp_imp).
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*/
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#define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */
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#define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */
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#define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */
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#define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */
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#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */
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#define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */
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#define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */
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#define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */
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#define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */
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#define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */
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#define MIPS_R4100 0x0c /* NEC VR41xx CPU MIPS-16 ISA III */
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#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
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#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
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#define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */
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#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */
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#define MIPS_R5000 0x23 /* MIPS R5000 CPU ISA IV */
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#define MIPS_RM7000 0x27 /* QED RM7000 CPU ISA IV */
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#define MIPS_RM52X0 0x28 /* QED RM52X0 CPU ISA IV */
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#define MIPS_E9000 0x34 /* PMC-Sierra E9000 core (RM9k) ISA IV */
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#define MIPS_VR5400 0x54 /* NEC Vr5400 CPU ISA IV+ */
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#define MIPS_GODSON3 0x63 /* Godson 2 CPU change_by_sizhiying*/
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#define MIPS_GODSON1 0x42 /* Godson 1 CPU */
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/*
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* MIPS FPU types
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*/
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#define MIPS_SOFT 0x00 /* Software emulation ISA I */
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#define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */
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#define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */
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#define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */
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#define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */
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#define MIPS_R4010 0x05 /* MIPS R4000/R4400 FPC ISA II */
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#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */
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#define MIPS_R10010 0x09 /* MIPS R10000/T5 FPU ISA IV */
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#define MIPS_R4210 0x0a /* MIPS R4200 FPC (ICE) ISA III */
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#define MIPS_UNKF1 0x0b /* unnanounced product cpu ISA III */
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#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
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#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
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#define MIPS_R3SONY 0x21 /* Sony R3000 based FPU ISA I */
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#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */
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#define MIPS_R5010 0x23 /* MIPS R5000 based FPU ISA IV */
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#define MIPS_RM7000 0x27 /* QED RM7000 FPU ISA IV */
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#define MIPS_RM5230 0x28 /* QED RM52X0 based FPU ISA IV */
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#define MIPS_RM52XX 0x28 /* QED RM52X0 based FPU ISA IV */
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#define MIPS_VR5400 0x54 /* NEC Vr5400 FPU ISA IV+ */
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#if defined(_KERNEL) && !defined(_LOCORE)
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union cpuprid CpuProcessorId;
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u_int CpuPrimaryInstCacheSize;
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u_int CpuPrimaryInstCacheLSize;
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u_int CpuPrimaryInstSetSize;
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u_int CpuPrimaryDataCacheSize;
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u_int CpuPrimaryDataCacheLSize;
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u_int CpuPrimaryDataSetSize;
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u_int CpuCacheAliasMask;
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u_int CpuSecondaryCacheSize;
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u_int CpuTertiaryCacheSize;
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u_int CpuNWayCache;
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u_int CpuCacheType; /* R4K, R5K, RM7K */
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u_int CpuConfigRegister;
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u_int CpuStatusRegister;
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u_int CpuExternalCacheOn; /* R5K, RM7K */
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u_int CpuOnboardCacheOn; /* RM7K */
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struct tlb;
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struct user;
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void flushcache __P((void));
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void flushicache __P((void *, size_t));
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void flushdcache __P((void *, size_t));
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void syncicache __P((void *, size_t));
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void delay __P((int));
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int CPU_ConfigCache __P((void));
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void CPU_SetWIRED __P((int));
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void CPU_SetPID __P((int));
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u_int CPU_GetCOUNT __P((void));
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u_int CPU_GetCONFIG __P((void));
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void CPU_SetCOMPARE __P((u_int));
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int CPU_SetSR __P((u_int, u_int));
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void CPU_FlushCache __P((void));
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void CPU_FlushDCache __P((vm_offset_t, int));
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void CPU_HitFlushDCache __P((vm_offset_t, int));
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void CPU_IOFlushDCache __P((vm_offset_t, int, int));
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void CPU_HitInvalidateDCache __P((vm_offset_t, int));
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void CPU_FlushICache __P((vm_offset_t, int));
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void CPU_InvalidateICache __P((vm_offset_t, int));
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void CPU_TLBFlush __P((int));
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void CPU_TLBFlushAddr __P((vm_offset_t));
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void CPU_TLBWriteIndexed __P((int, struct tlb *));
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void CPU_TLBUpdate __P((vm_offset_t, unsigned));
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void CPU_TLBRead __P((int, struct tlb *));
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void wbflush __P((void));
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void savectx __P((struct user *, int));
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int copykstack __P((struct user *));
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void switch_exit __P((void));
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void MipsSaveCurFPState __P((struct proc *));
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extern u_int32_t cpu_counter_interval; /* Number of counter ticks/tick */
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extern u_int32_t cpu_counter_last; /* Last compare value loaded */
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#else
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#ifndef _LOCORE
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void delay __P((int));
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#endif
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#endif /* _KERNEL */
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#endif /* !_MIPS_CPU_H_ */
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