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691 lines
24 KiB
691 lines
24 KiB
/*
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* This is userland program. This opens the network interface and attaches a data gram socket.
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* The communication to the hardware is accomplished through the Ioctl's sent through the
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* datagram socket.
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*/
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/* sw
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#include <stdio.h>
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#define ENH_DESC_8W //comment this if intended to use normal descriptor or 4 words
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#include <sys/types.h>
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#include <sys/socket.h>
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#include <linux/sockios.h>
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#include <string.h>
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#include <linux/netdevice.h>
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*/
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#include "GMAC_Pmon.h"
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#define IOCTL_READ_REGISTER SIOCDEVPRIVATE+1
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#define IOCTL_WRITE_REGISTER SIOCDEVPRIVATE+2
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#define IOCTL_READ_IPSTRUCT SIOCDEVPRIVATE+3
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#define IOCTL_READ_RXDESC SIOCDEVPRIVATE+4
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#define IOCTL_READ_TXDESC SIOCDEVPRIVATE+5
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#define IOCTL_POWER_DOWN SIOCDEVPRIVATE+6
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typedef unsigned long long u64;
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typedef unsigned long u32;
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typedef unsigned short u16;
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typedef unsigned char u8;
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typedef signed long long s64;
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typedef signed long s32;
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typedef signed short s16;
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typedef signed char s8;
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typedef int bool;
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typedef unsigned long dma_addr_t;
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struct ifr_data_struct
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{
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u32 unit;
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u32 addr;
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u32 data;
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};
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struct reg
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{
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u32 addr;
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char * name;
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};
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enum WcsCmd
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{
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wcs_write = 1,
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wcs_set,
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wcs_clr
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};
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/*
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DMA Descriptor Structure
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The structure is common for both receive and transmit descriptors
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*/
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#ifdef ENH_DESC_8W
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typedef struct DmaDescStruct
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{
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u32 status; /* Status */
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u32 length; /* Buffer 1 and Buffer 2 length */
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u32 buffer1; /* Network Buffer 1 pointer (Dma-able) */
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u32 buffer2; /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure */
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/* This data below is used only by driver */
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u32 extstatus; /* Extended status of a Rx Descriptor */
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u32 reserved1; /* Reserved word */
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u32 timestamplow; /* Lower 32 bits of the 64 bit timestamp value */
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u32 timestamphigh; /* Higher 32 bits of the 64 bit timestamp value */
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u32 data1; /* This holds virtual address of buffer1, not used by DMA */
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u32 data2; /* This holds virtual address of buffer2, not used by DMA */
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} DmaDesc;
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#else
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typedef struct DmaDescStruct
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{ /* put it here to allow the caller to know its size */
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u32 status; /* Status */
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u32 length; /* Buffer length */
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u32 buffer1; /* Buffer 1 pointer */
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u32 buffer2; /* Buffer 2 pointer or next descriptor pointer in chain structure */
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u32 data1; /* driver data, are not used by DMA engine, */
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u32 data2; /* set DmaDescriptorSkip2 in DmaBusModeInit to skip these words */
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} DmaDesc;
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#endif
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/* synopGMACdevice data */
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typedef struct synopGMACDeviceStruct
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{
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u64 MacBase; /* base address of MAC registers */
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u64 DmaBase; /* base address of DMA registers */
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u32 PhyBase; /* PHY device address on MII interface */
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u32 Version; /* Gmac Revision version */
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dma_addr_t TxDescDma;
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dma_addr_t RxDescDma;
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DmaDesc *TxDesc; /* start of TX descriptors ring/chain */
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DmaDesc *RxDesc; /* start of RX descriptors ring/chain */
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u32 BusyTxDesc; /* Number of Tx Descriptors owned by DMA at any given time*/
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u32 BusyRxDesc; /* Number of Rx Descriptors owned by DMA at any given time*/
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u32 RxDescCount; /* number of rx descriptors */
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u32 TxDescCount; /* number of tx descriptors */
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u32 TxBusy; /* first descriptor owned by DMA engine, moved by DmaTxGet */
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u32 TxNext; /* next available tx descriptor, moved by DmaTxSet */
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u32 RxBusy; /* first descripror owned by DMA engine, moved by DmaRxGet */
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u32 RxNext; /* next available rx descriptor, moved by DmaRxSet */
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DmaDesc * TxBusyDesc; /* first descriptor owned by DMA engine, moved by DmaTxGet */
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DmaDesc * TxNextDesc; /* next available tx descriptor, moved by DmaTxSet */
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DmaDesc * RxBusyDesc; /* first descripror owned by DMA engine, moved by DmaRxGet */
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DmaDesc * RxNextDesc; /* next available rx descriptor, moved by DmaRxSet */
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/*Phy related stuff*/
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u32 ClockDivMdc;
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/* The status of the link */
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u32 LinkState;
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u32 DuplexMode;
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u32 Speed;
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u32 LoopBackMode;
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} synopGMACdevice;
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static struct reg mac[] =
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{
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{ 0x0000, " Config" },
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{ 0x0004, " Frame Filter" },
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{ 0x0008, " MAC HT High" },
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{ 0x000C, " MAC HT Low" },
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{ 0x0010, " GMII Addr" },
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{ 0x0014, " GMII Data" },
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{ 0x0018, " Flow Control" },
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{ 0x001C, " VLAN Tag" },
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{ 0x0020, " GMAC Version" },
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{ 0x0024, " GMAC Debug " },
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{ 0x0040, " MAC Addr0 High" },
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{ 0x0044, " MAC Addr0 Low" },
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{ 0x0048, " MAC Addr1 High" },
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{ 0x004c, " MAC Addr1 Low" },
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{ 0x0100, " MMC Ctrl Reg " },
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{ 0x010c, "MMC Intr Reg(rx)" },
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{ 0x0110, "MMC Intr Reg(tx)" },
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{ 0x0200, "MMC Intr Reg(rx ipc)" },
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{ 0, 0 }
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};
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static struct reg ts[] =
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{
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{ 0x0700, " TS Ctrl Reg" },
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{ 0x0704, "Sub Sec Incr Reg" },
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{ 0x0708, " TS High Reg" },
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{ 0x070C, " TS Low Reg" },
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{ 0x0710, "TS High Updt Reg" },
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{ 0x0714, "TS Low Updt Reg" },
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{ 0x0718, " TS Addend Reg" },
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{ 0x071C, "Tgt Time (H) Reg" },
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{ 0x0720, "Tgt Time (L) Reg" },
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{ 0x0724, "TS High Word Reg" },
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{ 0x0728, " TS Status Reg" },
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{ 0x072C, " TS PPS Ctrl Reg" },
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{ 0, 0 }
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};
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static struct reg dma[] =
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{
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{ 0x0000, "CSR0 Bus Mode" },
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{ 0x0004, "CSR1 TxPlDmnd" },
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{ 0x0008, "CSR2 RxPlDmnd" },
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{ 0x000C, "CSR3 Rx Base" },
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{ 0x0010, "CSR4 Tx Base" },
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{ 0x0014, "CSR5 Status" },
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{ 0x0018, "CSR6 Control" },
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{ 0x001C, "CSR7 Int Enable" },
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{ 0x0020, "CSR8 Missed Fr." },
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{ 0x0048, "CSR18 Tx Desc " },
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{ 0x004C, "CSR19 Rx Desc " },
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{ 0x0050, "CSR20 Tx Buffer" },
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{ 0x0054, "CSR21 Rx Buffer" },
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{ 0x0058, "CSR22 HWCFG " },
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{ 0, 0 }
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};
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static struct reg mii[] =
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{
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{ 0x0000, "Phy Control Reg" },
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{ 0x0001, "Phy Status Reg" },
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{ 0x0002, "Phy Id (02) " },
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{ 0x0003, "Phy Id (03) " },
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{ 0x0004, "Auto-nego Adv" },
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{ 0x0005, "Auto-nego Lpa" },
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{ 0x0006, "Auto-nego Exp" },
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{ 0x0007, "Auto-nego Np" },
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{ 0x0009, "1000 Ctl Reg" },
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{ 0x000a, "1000 Sts Reg" },
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{ 0x0010, "PHY Ctl Reg" },
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{ 0x0011, "PHY Sts Reg" },
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{ 0, 0 }
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};
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static struct reg mmc[] =
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{
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{ 0x0114, "No. Of Bytes Transmitted (Good/Bad) " },
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{ 0x0164, "No. Of Bytes Transmitted (Good) " },
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{ 0x0118, "No. Of Frames Trsnsmitted (Good/Bad) " },
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{ 0x0168, "No. Of Frames Trsnsmitted (Good) " },
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{ 0x013C, "No. Of Unicast Frames Transmitted (Good/Bad) " },
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{ 0x011C, "No. Of Broadcast Frames Transmitted (Good) " },
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{ 0x0140, "No. Of Broadcast Frames Transmitted (Good/Bad) " },
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{ 0x0120, "No. Of Multicast Frames Transmitted (Good) " },
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{ 0x0144, "No. Of Multicast Frames Transmitted (Good/Bad) " },
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{ 0x0124, "No. Of Tx frames with Length 64 bytes (Good/Bad) " },
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{ 0x0128, "No. Of Tx frames with Length <064,128> bytes (Good/Bad) " },
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{ 0x012C, "No. Of Tx frames with Length <128,256> bytes (Good/Bad) " },
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{ 0x0130, "No. Of Tx frames with Length <256,512> bytes (Good/Bad) " },
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{ 0x0134, "No. Of Tx frames with Length <512,1024> bytes (Good/Bad) " },
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{ 0x0138, "No. Of Tx frames with Length <1024,MaxSize> bytes (Good/Bad) " },
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{ 0x0148, "No. Of Tx aborted due to Underflow error " },
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{ 0x0158, "No. Of Tx aborted due to Late Collision " },
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{ 0x015C, "No. Of Tx aborted due to Excessive Collision " },
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{ 0x0160, "No. Of Tx aborted due to Carrier Sense error " },
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{ 0x016C, "No. Of Tx aborted due to Excessive Defferal error " },
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{ 0x014C, "No. Of Tx frames after single collision in Half Duplex mode " },
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{ 0x0150, "No. Of Tx frames after multiple collision in Half Duplex mode " },
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{ 0x0154, "No. Of Tx frames after a deferral " },
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{ 0x0170, "No. Of Pause frames Transmitted (Good) " },
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{ 0x0174, "No. Of VLAM tagged frames Transmitted (Good) " },
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{ 0x0184, "No. Of Bytes Received (Good/Bad) " },
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{ 0x0188, "No. Of Bytes Received (Good) " },
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{ 0x0180, "No. Of Frames Received (Good/Bad) " },
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{ 0x01C4, "No. Of Unicast Frames Received (Good) " },
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{ 0x018C, "No. Of Broadcast Frames Transmitted (Good) " },
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{ 0x0190, "No. Of Multicast Frames Transmitted (Good) " },
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{ 0x01AC, "No. Of Rx frames with Length 64 bytes (Good/Bad) " },
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{ 0x01B0, "No. Of Rx frames with Length <064,128> bytes (Good/Bad) " },
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{ 0x01B4, "No. Of Rx frames with Length <128,256> bytes (Good/Bad) " },
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{ 0x01B8, "No. Of Rx frames with Length <256,512> bytes (Good/Bad) " },
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{ 0x01BC, "No. Of Rx frames with Length <512,1024> bytes (Good/Bad) " },
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{ 0x01C0, "No. Of Rx frames with Length <1024,MaxSize> bytes (Good/Bad) " },
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{ 0x01A4, "No. Of Runt Rx frames with frames (<64) " },
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{ 0x01A8, "No. Of Jabber Rx frames with frames (>1518) " },
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{ 0x0194, "No. Of Rx frames with CRC error " },
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{ 0x0198, "No. Of Rx frames with dribble error (only in 10/100) " },
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{ 0x019C, "No. Of Rx frames with runt error (<64 and CRC error) " },
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{ 0x01A0, "No. Of Rx frames with jabber error (>1518 and CRC) " },
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{ 0x01D4, "No. Of Rx frames missed due to FIFO overflow " },
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{ 0x01DC, "No. Of Rx frames received with watchdog timeout error " },
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{ 0x01C8, "No. Of Rx frames with Length != Frame Size " },
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{ 0x01CC, "No. Of Rx frames with Length != Valid Frame Size " },
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{ 0x0170, "No. Of Pause frames Received (Good) " },
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{ 0x0174, "No. Of VLAM tagged frames Received (Good) " },
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{ 0x0210, "No. Of IPV4 Packets Received (Good) " },
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{ 0x021C, "No. Of IPV4 Packets with fragmentation Received " },
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{ 0x0220, "No. Of IPV4 Packets with UDP checksum disabled " },
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{ 0x0214, "No. Of IPV4 Packets with Header Error Received " },
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{ 0x0218, "No. Of IPV4 Packets with No Payload Error Received " },
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{ 0x0224, "No. Of IPV6 Packets Received (Good) " },
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{ 0x0228, "No. Of IPV4 Packets with Header Error Received " },
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{ 0x022C, "No. Of IPV6 Packets with No Payload Error Received " },
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{ 0x0240, "No. Of ICMP Frames Received (Good) " },
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{ 0x0244, "No. Of ICMP Frames Received with Error " },
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{ 0x0230, "No. Of UDP Frames Received (Good) " },
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{ 0x0234, "No. Of UDP Frames Received with Error " },
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{ 0x0238, "No. Of TCP Frames Received (Good) " },
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{ 0x023C, "No. Of TCP Frames Received with Error " },
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{ 0, 0 }
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};
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static char copyright[] =
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"\n"
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" ********************************************\n"
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" * synopGMAC debug Utility for Linux *\n"
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" * Copyright(c) 2007-2007 Synopsys, Inc *\n"
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" ********************************************\n\n"
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;
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static char usage[] =
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" Usage:\n"
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" synopGMAC_Debug <interface> <command> {<parameters>}\n"
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"\n"
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" Commands:\n"
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" dump <unit> - dump registers, unit ::= {mac|ts|dma|mii|mmc}\n"
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" read <unit> <reg> unit ::= {mac|ts|dma|mii}\n"
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" write/set/clr <unit> <reg> <value> unit ::= {mac|ts|dma|mii}\n"
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" - write/set/clr bits\n"
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" status - print driver's internal data and dump DMA descriptors\n"
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" powerdown <on/off>\n"
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"\n"
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;
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static int powerdown(char *ifname, int argc, char *argv[] )
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{
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int socket_desc;
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int retval = 0;
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struct ifreq ifr; //defined in if.h
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struct ifr_data_struct data;
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struct reg *regs;
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if(argc != 1) return 1;
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if ( strcmp( argv[0], "on" ) == 0 ) { data.unit = 1;}
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else if( strcmp( argv[0], "off" ) == 0 ) { data.unit = 2;}
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else return 1;
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socket_desc = socket( PF_INET, SOCK_DGRAM, 0 );
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if( socket_desc < 0 )
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{
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perror("Socket error");
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return -1;
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}
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strcpy( ifr.ifr_name, ifname );
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ifr.ifr_data = (void *) &data;
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retval = ioctl( socket_desc, IOCTL_POWER_DOWN, &ifr );
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if( retval < 0 )
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{
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printf("IOCTL Error");
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goto close_socket;
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}
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printf("The GMAC is Successfully powered %s\n", (( data.unit == 1 ) ? "Down":"Up" ) );
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close_socket: close(socket_desc);
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return retval;
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}
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static int dump( char *ifname, int argc, char *argv[] )
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{
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int socket_desc;
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int retval = 0;
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struct ifreq ifr; //defined in if.h
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struct ifr_data_struct data;
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struct reg *regs;
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if(argc!=1) return 1;
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if ( strcmp( argv[0], "mac" ) == 0 ) { data.unit = 0; regs = mac; }
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else if( strcmp( argv[0], "ts" ) == 0 ) { data.unit = 0; regs = ts; }
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else if( strcmp( argv[0], "dma" ) == 0 ) { data.unit = 1; regs = dma; }
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else if( strcmp( argv[0], "mii" ) == 0 ) { data.unit = 2; regs = mii; }
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else if( strcmp( argv[0], "mmc" ) == 0 ) { data.unit = 0; regs = mmc; }
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else return 1;
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printf("%s Dump %s Registers: \n", ifname, argv[0]);
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socket_desc = socket( PF_INET, SOCK_DGRAM, 0 );
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if( socket_desc < 0 )
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{
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perror("Socket error");
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return -1;
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}
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strcpy( ifr.ifr_name, ifname );
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ifr.ifr_data = (void *) &data;
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while( regs->name != 0 )
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{
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data.addr = regs->addr;
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retval = ioctl( socket_desc, IOCTL_READ_REGISTER, &ifr );
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if( retval < 0 )
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{
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printf("IOCTL Error");
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break;
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}
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printf( "%s (0x%04x) = 0x%08x\n", regs->name, regs->addr, data.data );
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regs++;
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}
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close(socket_desc);
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return retval;
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}
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static int read(char *ifname, int argc, char *argv[])
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{
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int socket_desc;
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int retval = 0;
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struct ifreq ifr; //defined in if.h
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struct ifr_data_struct data;
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struct reg *regs;
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if(argc != 2) return 1;
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if ( strcmp( argv[0], "mac" ) == 0 ) { data.unit = 0; regs = mac; }
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else if( strcmp( argv[0], "ts" ) == 0 ) { data.unit = 0; regs = ts; }
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else if( strcmp( argv[0], "dma" ) == 0 ) { data.unit = 1; regs = dma; }
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else if( strcmp( argv[0], "mii" ) == 0 ) { data.unit = 2; regs = mii; }
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else return 1;
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strcpy( ifr.ifr_name, ifname );
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ifr.ifr_data = (void *) &data;
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data.addr = strtol(argv[1],NULL,16); //convert the register address argument from string to long
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if(((data.unit == 0) && (data.addr > 0x000002FC)) || ((data.addr & 0x00000003) != 0))
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return 1;
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if(((data.unit == 1) && (data.addr > 0x00000058)) || ((data.addr & 0x00000003) != 0))
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return 1;
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if((data.unit == 2) && (data.addr > 0x0000001c))
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return 1;
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socket_desc = socket( PF_INET, SOCK_DGRAM, 0 );
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if( socket_desc < 0 )
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{
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perror("Socket error");
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return -1;
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}
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retval = ioctl( socket_desc, IOCTL_READ_REGISTER, &ifr );
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if(retval < 0)
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{
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printf("IOCTL Error");
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goto close_socket;
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}
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printf( "[%s](0x%04x) = 0x%08x\n ",argv[0],data.addr, data.data);
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|
|
close_socket: close(socket_desc);
|
|
return retval;
|
|
}
|
|
|
|
|
|
|
|
|
|
static int wcs(int cmd, char * ifname, char * cmdname, int argc, char *argv[])
|
|
{
|
|
int socket_desc;
|
|
int retval = 0;
|
|
struct ifreq ifr; //defined in if.h
|
|
|
|
struct ifr_data_struct data;
|
|
struct reg *regs;
|
|
u32 data_to_write;
|
|
|
|
if (argc != 3) return -1;
|
|
|
|
if (strcmp (argv[0],"mac") == 0){
|
|
data.unit = 0;
|
|
regs = mac;
|
|
}
|
|
else if (strcmp (argv[0],"ts") == 0){
|
|
data.unit = 0;
|
|
regs = ts;
|
|
}
|
|
else if (strcmp (argv[0],"dma") == 0){
|
|
data.unit = 1;
|
|
regs = dma;
|
|
}
|
|
else if (strcmp (argv[0],"mii") == 0){
|
|
data.unit = 2;
|
|
regs = mii;
|
|
}
|
|
else return -1;
|
|
|
|
sscanf(argv[1], "%x", &data.addr);
|
|
while(regs->name != 0){
|
|
if(regs->addr == data.addr) break;
|
|
regs++;
|
|
}
|
|
if(regs->name == 0){
|
|
printf("Invalid %s Register - 0x%02x\n",argv[0],data.addr);
|
|
return -1;
|
|
}
|
|
sscanf(argv[2],"%x", &data_to_write);
|
|
printf("%s %s 0x%08x to %s Register 0x%02x\n",ifname,cmdname,data_to_write,argv[0],data.addr);
|
|
|
|
socket_desc = socket( PF_INET, SOCK_DGRAM, 0 );
|
|
if( socket_desc < 0 )
|
|
{
|
|
perror("Socket error");
|
|
return -1;
|
|
}
|
|
|
|
strcpy( ifr.ifr_name, ifname );
|
|
ifr.ifr_data = (void *) &data;
|
|
|
|
if(cmd == wcs_set || cmd == wcs_clr){
|
|
retval = ioctl(socket_desc,IOCTL_READ_REGISTER, &ifr);
|
|
if(retval < 0){
|
|
perror("IOCTL Error");
|
|
}
|
|
}
|
|
|
|
if(retval == 0){
|
|
if(cmd == wcs_set ) data.data |= data_to_write;
|
|
if(cmd == wcs_clr) data.data &= (~data_to_write);
|
|
if(cmd == wcs_write) data.data = data_to_write;
|
|
}
|
|
|
|
retval = ioctl(socket_desc,IOCTL_WRITE_REGISTER, &ifr);
|
|
if(retval < 0)
|
|
perror("IOCTL Error");
|
|
|
|
close(socket_desc);
|
|
return retval;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
static int status(char * ifname, int argc, char *argv[])
|
|
{
|
|
int socket_desc;
|
|
int retval = 0;
|
|
int count = 0;
|
|
struct ifreq ifr; //defined in if.h
|
|
|
|
DmaDesc dmadesc;
|
|
synopGMACdevice gmacdev;
|
|
|
|
if(argc!=0) return 1;
|
|
|
|
printf("%s Dump Status: \n", ifname);
|
|
|
|
socket_desc = socket( PF_INET, SOCK_DGRAM, 0 );
|
|
if( socket_desc < 0 )
|
|
{
|
|
perror("Socket error");
|
|
return -1;
|
|
}
|
|
|
|
strcpy( ifr.ifr_name, ifname );
|
|
|
|
ifr.ifr_data = (void *) &gmacdev;
|
|
|
|
retval = ioctl( socket_desc, IOCTL_READ_IPSTRUCT, &ifr );
|
|
|
|
if( retval < 0 )
|
|
{
|
|
printf("IOCTL Error");
|
|
}
|
|
|
|
else
|
|
{
|
|
printf("GMAC ip Version = 0x%08x\n", gmacdev.Version );
|
|
printf("GMAC Register Base Address = 0x%08x\n", gmacdev.MacBase );
|
|
printf("DMA Register Base Address = 0x%08x\n", gmacdev.DmaBase );
|
|
printf("PHY device Base Address(32 phys possible) = 0x%08x\n", gmacdev.PhyBase );
|
|
printf("Start of Rx Desc Ring = %p\n", gmacdev.RxDesc );
|
|
printf("Start of Tx Desc Ring = %p\n", gmacdev.TxDesc );
|
|
|
|
printf("Busy Rx Desc Count = %d\n", gmacdev.BusyRxDesc );
|
|
printf("Busy Tx Desc Count = %d\n", gmacdev.BusyTxDesc );
|
|
|
|
printf("Start of Rx Desc Ring(DMA) = %p\n", gmacdev.RxDescDma );
|
|
printf("Start of Tx Desc Ring(DMA) = %p\n", gmacdev.TxDescDma );
|
|
printf("Number of Rx Descriptors = %d\n", gmacdev.RxDescCount );
|
|
printf("Number of Tx Descriptors = %d\n", gmacdev.TxDescCount );
|
|
printf("First Rx Descriptor Owned by DMA Engine = %d\n", gmacdev.RxBusy );
|
|
printf("Next Available Rx Descriptor = %d\n", gmacdev.RxNext );
|
|
printf("First Tx Descriptor Owned by DMA Engine = %d\n", gmacdev.TxBusy );
|
|
printf("Next Available Tx Descriptor = %d\n", gmacdev.TxNext );
|
|
printf("MDC clock division number = 0x%08x\n", gmacdev.ClockDivMdc);
|
|
printf("Link State information = 0x%08x\n", gmacdev.LinkState );
|
|
printf("Duplex Mode of the Interface = 0x%08x\n", gmacdev.DuplexMode );
|
|
printf("Speed of the Interface = 0x%08x\n", gmacdev.Speed );
|
|
printf("LoopBack status of the Interface = 0x%08x\n", gmacdev.LoopBackMode);
|
|
|
|
printf("\n");
|
|
#ifdef ENH_DESC
|
|
printf("RxD Idx: Status length buffer1 buffer2 data1 data2 Ext_status reserved TSL TSH \n");
|
|
printf("---------------------------------------------------------------------------------------------------------------------------- \n");
|
|
for(count = 0; count < gmacdev.RxDescCount; count++ ){
|
|
dmadesc.data1 = count;
|
|
ifr.ifr_data = (void *) &dmadesc;
|
|
retval = ioctl(socket_desc, IOCTL_READ_RXDESC,&ifr);
|
|
if(retval < 0)
|
|
break;
|
|
printf("RxD %02x: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
|
|
count,dmadesc.status, dmadesc.length,dmadesc.buffer1,dmadesc.buffer2,
|
|
dmadesc.data1,dmadesc.data2,dmadesc.extstatus,dmadesc.reserved1,dmadesc.timestamplow,dmadesc.timestamphigh);
|
|
}
|
|
if(retval < 0)
|
|
perror("IOCTL Error");
|
|
|
|
printf("\n");
|
|
|
|
printf("TxD Idx: Status length buffer1 buffer2 data1 data2 reserved reserved TSL TSH \n");
|
|
printf("---------------------------------------------------------------------------------------------------------------------------- \n");
|
|
for(count = 0; count < gmacdev.TxDescCount; count++ ){
|
|
dmadesc.data1 = count;
|
|
ifr.ifr_data = (void *) &dmadesc;
|
|
retval = ioctl(socket_desc, IOCTL_READ_TXDESC,&ifr);
|
|
if(retval < 0)
|
|
break;
|
|
printf("TxD %02x: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
|
|
count,dmadesc.status, dmadesc.length,dmadesc.buffer1,dmadesc.buffer2,
|
|
dmadesc.data1,dmadesc.data2,dmadesc.extstatus,dmadesc.reserved1,dmadesc.timestamplow,dmadesc.timestamphigh);
|
|
}
|
|
if(retval < 0)
|
|
perror("IOCTL Error");
|
|
#else
|
|
printf("RxD Idx: Status length buffer1 buffer2 data1 data2 \n");
|
|
printf("---------------------------------------------------------------------------\n");
|
|
for(count = 0; count < gmacdev.RxDescCount; count++ ){
|
|
dmadesc.data1 = count;
|
|
ifr.ifr_data = (void *) &dmadesc;
|
|
retval = ioctl(socket_desc, IOCTL_READ_RXDESC,&ifr);
|
|
if(retval < 0)
|
|
break;
|
|
printf("RxD %02x: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
|
|
count,dmadesc.status, dmadesc.length,dmadesc.buffer1,dmadesc.buffer2,
|
|
dmadesc.data1,dmadesc.data2);
|
|
}
|
|
if(retval < 0)
|
|
perror("IOCTL Error");
|
|
|
|
printf("\n");
|
|
|
|
printf("TxD Idx: Status length buffer1 buffer2 data1 data2 \n");
|
|
printf("-----------------------------------------------------------------------------\n");
|
|
for(count = 0; count < gmacdev.TxDescCount; count++ ){
|
|
dmadesc.data1 = count;
|
|
ifr.ifr_data = (void *) &dmadesc;
|
|
retval = ioctl(socket_desc, IOCTL_READ_TXDESC,&ifr);
|
|
if(retval < 0)
|
|
break;
|
|
printf("TxD %02x: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x \n",
|
|
count,dmadesc.status, dmadesc.length,dmadesc.buffer1,dmadesc.buffer2,
|
|
dmadesc.data1,dmadesc.data2);
|
|
}
|
|
if(retval < 0)
|
|
perror("IOCTL Error");
|
|
#endif
|
|
}
|
|
close(socket_desc);
|
|
return 0;
|
|
|
|
}
|
|
|
|
int main( int argc, char *argv[] )
|
|
{
|
|
int retval = 1;
|
|
|
|
printf(copyright);
|
|
|
|
if( argc>=3 )
|
|
{
|
|
// if( strcmp( argv[2], "debug" ) == 0 ) retval = debug( argv[1], argc-3, argv+3 );
|
|
if( strcmp( argv[2], "dump" ) == 0 ) retval = dump( argv[1], argc-3, argv+3 );
|
|
if( strcmp( argv[2], "write" ) == 0 ) retval = wcs( wcs_write, argv[1], argv[2], argc-3, argv+3 );
|
|
if( strcmp( argv[2], "read" ) == 0 ) retval = read( argv[1], argc-3, argv+3 );
|
|
if( strcmp( argv[2], "set" ) == 0 ) retval = wcs( wcs_set, argv[1], argv[2], argc-3, argv+3 );
|
|
if( strcmp( argv[2], "clr" ) == 0 ) retval = wcs( wcs_clr, argv[1], argv[2], argc-3, argv+3 );
|
|
if( strcmp( argv[2], "status" ) == 0 ) retval = status( argv[1], argc-3, argv+3 );
|
|
if( strcmp( argv[2], "powerdown") == 0) retval = powerdown(argv[1],argc-3,argv+3);
|
|
}
|
|
|
|
if( retval==1 ) printf( usage );
|
|
return retval;
|
|
}
|
|
|