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349 lines
11 KiB
349 lines
11 KiB
/* $Id: if_gtx.h,v 1.1.1.1 2006/09/14 01:59:08 root Exp $ */
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/*
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* Copyright (c) 2001 Allegro Networks (www.allegronetworks.com)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Allegro Networks Inc.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#ifndef _IF_GTX_H
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#define _IF_GTX_H
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#include <target/pmon_target.h>
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#if defined(POWERPC)
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/* PPC uses the VA_TO_PA to get the physical address of the on-chip SRAM */
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#define OCRAM_TO_PA(x) VA_TO_PA(x)
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#elif defined(MIPS)
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/* MIPS maps the on-chip SRAM into the I/O space starting at 0xf0000000 */
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/* Note that PA_TO_VA() works fine here, but mostly by accident... */
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#define OCRAM_TO_PA(x) ((int)(x))
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#else
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#error OCRAM_TO_PA needs to be defined for this architecure!
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#endif
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/* Keep the ring sizes a power of two for efficiency. */
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#define TX_RING_SIZE 8
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#define RX_RING_SIZE 32
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#define RX_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
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#define TX_BUF_SZ 1536 /* Size of each temporary Tx buffer.*/
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/* Serial Control Register */
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#define PSCR_PORTEN (1 << 0)
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#define PSCR_FORCE_LINK_PASS (1 << 1)
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#define PSCR_DIS_AN_DUPLEX (1 << 2)
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#define PSCR_DIS_AN_FC (1 << 3)
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#define PSCR_PAUSE_ADV (1 << 4)
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#define PSCR_FORCE_FC_MODE(n) (((n) & 3) << 5)
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#define PSCR_FORCE_BP_MODE(n) (((n) & 3) << 7)
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#define PSCR_DIS_FORCE_LINK_FAIL (1 << 10)
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#define PSCR_RETR_FOREVER (1 << 11)
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#define PSCR_DIS_AN_SPEED (1 << 13)
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#define PSCR_DTE_ADVERT (1 << 14)
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#define PSCR_AN_BYPASS_EN (1 << 15)
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#define PSCR_RESTART_AN (1 << 16)
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#define PSCR_MRU(n) (((n) & 7) << 17)
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#define PSCR_SET_FULLDX (1 << 21)
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#define PSCR_SET_FC_EN (1 << 22)
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#define PSCR_SET_GMII_SPEED (1 << 23)
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#define PSCR_SET_MII_SPEED (1 << 24)
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#define PSCR_DEFAULT_SETTING \
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(PSCR_FORCE_LINK_PASS | PSCR_DIS_AN_FC | PSCR_PAUSE_ADV | 0x200 | \
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PSCR_DIS_FORCE_LINK_FAIL | PSCR_MRU(2) | PSCR_SET_FULLDX | PSCR_SET_FC_EN)
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/* Bit definitions of the SMI Reg */
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#define SMI_PHYAD_0(n) (((n) & 0x1f) << 0)
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#define SMI_PHYAD_1(n) (((n) & 0x1f) << 5)
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#define SMI_PHYAD_2(n) (((n) & 0x1f) << 10)
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#define SMI_DATA(n) (((n) & 0xffff) << 0)
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#define SMI_PHYAD(n) (((n) & 0x1f) << 16)
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#define SMI_REGAD(n) (((n) & 0x1f) << 21)
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#define SMI_READ (1 << 26)
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#define SMI_WRITE (0 << 26)
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#define SMI_READVALID (1 << 27)
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#define SMI_BUSY (1 << 28)
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/* Bit definitions of the Port Config Reg */
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#define PCR_UPM 1
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#define PCR_RXQ(n) (((n) & 3) << 1)
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#define PCR_RXQARP(n) (((n) & 7) << 4)
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#define PCR_RB (1 << 7)
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#define PCR_RBIP (1 << 8)
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#define PCR_RARP (1 << 9)
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#define PCR_AMNOTXES (1 << 12)
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#define PCR_TCP_CAPEN (1 << 14)
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#define PCR_UDP_CAPEN (1 << 15)
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#define PCR_TCPQ(n) (((n) & 7) << 16)
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#define PCR_UDPQ(n) (((n) & 7) << 19)
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#define PCR_BPDUQ(n) (((n) & 7) << 22)
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#define PCR_DEFAULT_SETTING \
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(PCR_RXQ(0) | PCR_RXQARP(0) | PCR_TCPQ(0) | PCR_UDPQ(0) | PCR_BPDUQ(0))
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/* Bit definitions of the Port Config Extend Reg */
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#define PCXR_SPAN (1 << 1)
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#define PCXR_PAREN (1 << 2)
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#define PCXR_DEFAULT_SETTING 0
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/* Bit definitions of the Port Command Reg */
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/* Bit definitions of the Port Status Reg */
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/* Bit definitions of the SDMA Config Reg */
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#define SDCR_RIFB (1 << 0)
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#define SDCR_RXBSZ(n) (((n) & 7) << 1)
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#define SDCR_BLMR (1 << 4)
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#define SDCR_BLMT (1 << 5)
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#define SDCR_SWAPMODE (1 << 6)
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#define SDCR_IGP_INT_RX(n) (((n) & 0x3fff) << 8)
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#define SDCR_TXBSZ(n) (((n) & 7) << 22)
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#define SDCR_BLMRT (SDCR_BLMR | SDCR_BLMT)
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#define SDCR_DEFAULT_SETTING \
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(SDCR_RXBSZ(4) | SDCR_IGP_INT_RX(0) | SDCR_TXBSZ(4))
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/* Bit definitions of the SDMA Command Reg */
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/* Bit definitions of the Interrupt Cause Reg */
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#define ICR_RXBUFFER (1 << 0)
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#define ICR_EXTEND (1 << 1)
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#define ICR_RXBUFFERQ(n) ((1 << ((n) & 7)) << 2)
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#define ICR_RXERROR (1 << 10)
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#define ICR_RXERRORQ(n) ((1 << ((n) & 7)) << 11)
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#define ICR_RTXEND (0xff << 19)
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#define ICR_TXEND(n) ((1 << ((n) & 7)) << 19)
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#define ICR_ETHERINTSUM (1 << 31)
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#define XICR_TXBUFF(n) ((1 << ((n) & 7)) << 0)
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#define XICR_TXERROR(n) ((1 << ((n) & 7)) << 8)
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#define XICR_PHYSTC (1 << 16)
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#define XICR_RXOVR (1 << 18)
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#define XICR_TXUDR (1 << 19)
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#define XICR_LINKCAHNGE (1 << 20)
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#define XICR_PARTITION (1 << 21)
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#define XICR_AUTONEGDONE (1 << 22)
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#define XICR_INTERNAL_ADDR_ERROR (1 << 23)
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#define XICR_ETHER_INT_SUM (1 << 31)
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/*
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* The Rx and Tx descriptor lists. (funny swapping rules...)
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*/
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#if BYTE_ORDER == LITTLE_ENDIAN
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typedef struct {
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u_int32_t cmdstat;
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u_int16_t l4_chk;
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u_int16_t byte_cnt;
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u_int32_t buff_ptr;
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u_int32_t next;
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char *vbuff_ptr;
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u_int32_t pad[3];
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} TX_DESC;
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typedef struct {
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u_int32_t cmdstat;
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u_int16_t buf_size;
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u_int16_t byte_cnt;
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u_int32_t buff_ptr;
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u_int32_t next;
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struct mbuf *rx_mbuf;
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char *vbuff_ptr;
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u_int32_t pad[2];
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} RX_DESC;
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#else
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typedef struct {
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u_int16_t byte_cnt;
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u_int16_t l4_chk;
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u_int32_t cmdstat;
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u_int32_t next;
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u_int32_t buff_ptr;
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char *vbuff_ptr;
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u_int32_t pad[3];
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} TX_DESC;
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typedef struct {
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u_int16_t byte_cnt;
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u_int16_t buf_size;
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u_int32_t cmdstat;
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u_int32_t next;
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u_int32_t buff_ptr;
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struct mbuf *rx_mbuf;
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char *vbuff_ptr;
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u_int32_t pad[2];
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} RX_DESC;
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#endif
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/* Values for the Tx command-status descriptor entry. */
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#define TX_O (1<<31)
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#define TX_AM (1<<30)
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#define TX_EI (1<<23)
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#define TX_GC (1<<22)
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#define TX_F (1<<21)
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#define TX_L (1<<20)
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#define TX_P (1<<19)
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#define TX_GIPCHK (1<<18)
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#define TX_GL4CHK (1<<17)
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#define TX_L4TYPE (1<<16)
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#define TX_VLAN (1<<15)
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#define TX_IPV4HDLEN (0x0f<<11)
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#define TX_L4CHK_MODE (1<<10)
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#define TX_LLC_SNAP (1<<9)
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#define TX_EC (3<<1)
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#define TX_ES (1<<0)
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/* Values for the Rx command-status descriptor entry. */
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#define RX_O (1<<31)
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#define RX_L4CHKOK (1<<30)
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#define RX_EI (1<<29)
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#define RX_U (1<<28)
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#define RX_F (1<<27)
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#define RX_L (1<<26)
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#define RX_IPHEADOK (1<<25)
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#define RX_L3IP (1<<24)
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#define RX_LAYER2EV2 (1<<23)
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#define RX_LAYER4 (3<<21)
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#define RX_BPDU (1<<20)
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#define RX_VLAN (1<<19)
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#define RX_L4CHK (0xffff<<3)
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#define RX_EC (3<<1)
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#define RX_ES 1
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/* Bit fields of a Hash Table Entry */
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enum hash_table_entry {
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hteValid = 1,
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hteSkip = 2,
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hteRD = 4
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};
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// The GT643x0 MIB counters
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typedef struct {
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u_int32_t bytesReceived;
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u_int32_t bytesSent;
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u_int32_t framesReceived;
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u_int32_t framesSent;
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u_int32_t totalBytesReceived;
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u_int32_t totalFramesReceived;
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u_int32_t broadcastFramesReceived;
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u_int32_t multicastFramesReceived;
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u_int32_t CRCErrors;
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u_int32_t oversizeFrames;
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u_int32_t fragments;
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u_int32_t jabber;
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u_int32_t collisions;
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u_int32_t lateCollisions;
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u_int32_t frames64_bytes;
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u_int32_t frames65_127_bytes;
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u_int32_t frames128_255_bytes;
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u_int32_t frames256_511_bytes;
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u_int32_t frames512_1023_bytes;
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u_int32_t frames1024_MaxSize;
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u_int32_t rxErrors;
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u_int32_t droppedFrames;
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u_int32_t multicastFramesSent;
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u_int32_t broadcastFramesSent;
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u_int32_t undersizeFrames;
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} mib_counters_t;
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/*
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* Network device statistics. Akin to the 2.0 ether stats but
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* with byte counters.
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*/
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struct net_device_stats
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{
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unsigned long rx_packets; /* total packets received */
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unsigned long tx_packets; /* total packets transmitted */
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unsigned long rx_bytes; /* total bytes received */
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unsigned long tx_bytes; /* total bytes transmitted */
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unsigned long rx_errors; /* bad packets received */
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unsigned long tx_errors; /* packet transmit problems */
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unsigned long rx_dropped; /* no space in linux buffers */
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unsigned long tx_dropped; /* no space available in linux */
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unsigned long multicast; /* multicast packets received */
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unsigned long collisions;
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/* detailed rx_errors: */
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unsigned long rx_length_errors;
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unsigned long rx_over_errors; /* receiver ring buff overflow */
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unsigned long rx_crc_errors; /* recved pkt with crc error */
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unsigned long rx_frame_errors; /* recv'd frame alignment error */
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unsigned long rx_fifo_errors; /* recv'r fifo overrun */
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unsigned long rx_missed_errors; /* receiver missed packet */
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/* detailed tx_errors */
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unsigned long tx_aborted_errors;
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unsigned long tx_carrier_errors;
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unsigned long tx_fifo_errors;
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unsigned long tx_heartbeat_errors;
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unsigned long tx_window_errors;
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/* for cslip etc */
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unsigned long rx_compressed;
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unsigned long tx_compressed;
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};
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struct gtx_softc {
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struct device sc_dev; /* Generic device structures */
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void *sc_ih; /* Interrupt handler cookie */
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bus_space_tag_t sc_st; /* Bus space tag */
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bus_space_handle_t sc_sh; /* Bus space handle */
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pci_chipset_tag_t sc_pc; /* Chipset handle needed by mips */
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struct arpcom arpcom; /* Per interface network data */
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RX_DESC *rx_ring;
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TX_DESC *tx_ring;
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u_int32_t *rx_hash;
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int sc_port; /* Easy access port number */
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int hash_mode;
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/*
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* Tx buffers with less than 8 bytes
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* of payload must be 8-byte aligned
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*/
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u_int8_t* tx_buff;
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u_int8_t* rx_buff;
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int rx_next_out; /* The next free ring entry to receive */
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int tx_next_in; /* The next free ring entry to send */
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int tx_next_out; /* The last ring entry the ISR processed */
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int tx_count; /* Packets waiting to be sent in Tx ring */
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int tx_queued;
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int tx_full; /* Tx ring is full */
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mib_counters_t mib;
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struct net_device_stats stats;
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int chip_rev;
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int phy_addr; /* PHY address */
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unsigned char phys[2]; /* MII device addresses */
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};
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#endif /* !_IF_GTX_H_ */
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