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85 lines
3.6 KiB
85 lines
3.6 KiB
/* $Id: mc146818reg.h,v 1.1.1.1 2006/09/14 01:59:08 root Exp $ */
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/*
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* Copyright (c) 2002 Opsycon AB (www.opsycon.se / www.opsycon.com)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Opsycon AB, Sweden.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#ifndef _DS_17285REG_H_
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#define _DS_17285REG_H_
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/*
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* Register definitions for Dallas Semiconductor DS17285/287 clock chips.
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*/
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#define DS_REG_SEC 0x00 /* Seconds reg */
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#define DS_REG_ASEC 0x01 /* Alarm Seconds reg */
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#define DS_REG_MIN 0x02 /* Minutes reg */
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#define DS_REG_AMIN 0x03 /* Alarm Minutes reg */
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#define DS_REG_HOUR 0x04 /* Hours reg */
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#define DS_REG_AHOUR 0x05 /* Alarm Hours reg */
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#define DS_REG_WDAY 0x06 /* Day of week reg */
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#define DS_REG_DATE 0x07 /* Day of month reg */
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#define DS_REG_MONTH 0x08 /* Month reg */
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#define DS_REG_YEAR 0x09 /* Year reg */
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#define DS_REG_CTLA 0x0a /* Control reg A */
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#define DS_REG_CTLB 0x0b /* Control reg B */
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#define DS_REG_CTLC 0x0c /* Control reg A */
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#define DS_REG_CTLD 0x0d /* Control reg B */
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#define DS_MONTH_E32K 0x40 /* Enable 32Khz out when 0 */
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#define DS_MONTH_EOSC 0x80 /* Enable oscilator when 0 */
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#define DS_CTLA_RS0 0x01 /* Rate Select */
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#define DS_CTLA_RS1 0x02 /* Rate Select */
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#define DS_CTLA_RS2 0x04 /* Rate Select */
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#define DS_CTLA_RS3 0x08 /* Rate Select */
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#define DS_CTLA_DV0 0x10 /* Bank Select */
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#define DS_CTLA_DV1 0x20 /* Osc. Enable */
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#define DS_CTLA_DV2 0x40 /* Countdown Chain */
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#define DS_CTLA_UIP 0x80 /* Update In Progress flag 1 */
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#define DS_CTLB_DSE 0x01 /* Daylight savings enable */
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#define DS_CTLB_24 0x02 /* 24hr enable */
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#define DS_CTLB_DM 0x04 /* Data mode */
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#define DS_CTLB_SQWE 0x08 /* Square wave enable */
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#define DS_CTLB_UIE 0x10 /* Update ended interrupt enable */
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#define DS_CTLB_AIE 0x20 /* Alarm interrupt enable */
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#define DS_CTLB_PIE 0x40 /* Periodic interrupt enable */
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#define DS_CTLB_SET 0x80 /* Set registers enable */
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/*
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* Registers in Bank 1
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*/
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#define DS_EXRAM_LSB 0x50 /* Extended RAM LSB addr */
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#define DS_EXRAM_MSB 0x51 /* Extended RAM MSB addr */
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#define DS_EXRAM_DATA 0x53 /* Extended RAM Data port */
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#endif /* _DS_17285REG_H_ */
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