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597 lines
16 KiB
597 lines
16 KiB
/* $XFree86: xc/programs/Xserver/hw/xfree86/int10/generic.c,v 1.21 2001/05/15 10:19:41 eich Exp $ */
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/*
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* XFree86 int10 module
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* execute BIOS int 10h calls in x86 real mode environment
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* Copyright 1999 Egbert Eich
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*/
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#define _INT10_PRIVATE
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#include <stdio.h>
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#include <stdlib.h>
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#include <dev/pci/pcivar.h>
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#include "xf86int10.h"
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#include "xf86x86emu.h"
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#include "linux/io.h"
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#include "mod_framebuffer.h"
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#include "vesa.h"
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#define vgaram_base (VGA_BASE + 0xa0000)
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#define ALLOC_ENTRIES(x) ((V_RAM / x) - 1)
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static CARD8 read_b(xf86Int10InfoPtr pInt, int addr);
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static CARD16 read_w(xf86Int10InfoPtr pInt, int addr);
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static CARD32 read_l(xf86Int10InfoPtr pInt, int addr);
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static void write_b(xf86Int10InfoPtr pInt, int addr, CARD8 val);
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static void write_w(xf86Int10InfoPtr pInt, int addr, CARD16 val);
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static void write_l(xf86Int10InfoPtr pInt, int addr, CARD32 val);
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/*
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* the emulator cannot pass a pointer to the current xf86Int10InfoRec
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* to the memory access functions therefore store it here.
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*/
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typedef struct {
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int shift;
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int entries;
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void *base;
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void *vRam;
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void *sysMem;
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char *alloc;
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} genericInt10Priv;
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#define INTPriv(x) ((genericInt10Priv*)x->private)
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int10MemRec genericMem = {
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read_b,
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read_w,
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read_l,
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write_b,
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write_w,
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write_l
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};
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static void *sysMem = NULL;
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#define CRT_C 24 /* 24 CRT Controller Registers */
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#define ATT_C 21 /* 21 Attribute Controller Registers */
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#define GRA_C 9 /* 9 Graphics Controller Registers */
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#define SEQ_C 5 /* 5 Sequencer Registers */
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#define MIS_C 1 /* 1 Misc Output Register */
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/* VGA registers saving indexes */
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#define CRT 0 /* CRT Controller Registers start */
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#define ATT (CRT+CRT_C) /* Attribute Controller Registers start */
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#define GRA (ATT+ATT_C) /* Graphics Controller Registers start */
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#define SEQ (GRA+GRA_C) /* Sequencer Registers */
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#define MIS (SEQ+SEQ_C) /* General Registers */
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#define EXT (MIS+MIS_C) /* SVGA Extended Registers */
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static void vgadelay(void)
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{
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int i;
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for (i = 0; i < 10; i++) ;
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}
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static unsigned char regs[60] = {
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0x5F, 0x4F, 0x50, 0x02, 0x55, 0x81, 0xBF, 0x1F, /* CR00-CR18 */
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0x00, 0x4F, 0x0D, 0x0E, 0x0, 0x0, 0x0, 0x0,
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0x9C, 0x00, 0x8F, 0x28, 0x1F, 0x96, 0xB9, 0xA3,
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0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* AR00-AR15 */
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0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
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0x0C, 0x00, 0x0F, 0x08, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0E, 0x00, /* GR00-GR05 */
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0xFF,
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0x03, 0x00, 0x03, 0x00, 0x02, /* SR00-SR05 */
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0x67, /* MISC_OUT */
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};
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static void outseq(int index, unsigned char val)
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{
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linux_outb(index, 0x3c4);
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linux_outb(val, 0x3c5);
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}
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static unsigned char inseq(unsigned char index)
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{
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linux_outb(index, 0x3c4);
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return linux_inb(0x3c5);
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}
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static void outcrtc(int index, unsigned char val)
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{
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linux_outb(index, 0x3d4);
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linux_outb(val, 0x3d5);
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}
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static unsigned char incrtc(int index)
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{
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linux_outb(index, 0x3d4);
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return linux_inb(0x3d5);
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}
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static void outgra(int index, unsigned char val)
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{
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linux_outb(index, 0x3ce);
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linux_outb(val, 0x3cf);
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}
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static unsigned char ingra(int index)
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{
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linux_outb(index, 0x3ce);
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return linux_inb(0x3cf);
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}
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static void outatt(int index, unsigned char val)
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{
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linux_inb(0x3da);
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vgadelay();
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linux_outb(index, 0x3c0);
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vgadelay();
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linux_outb(val, 0x3c0);
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vgadelay();
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}
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static unsigned char inatt(int index)
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{
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linux_inb(0x3da);
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vgadelay();
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linux_outb(index, 0x3c0);
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vgadelay();
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return linux_inb(0x3c1);
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}
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static void setregs(const unsigned char *regs)
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{
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int i;
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unsigned char val;
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// misc
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linux_outb(regs[MIS], 0x3c2);
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// seq
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outseq(0x0, 0x1);
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outseq(0x01, regs[SEQ + 1] | 0x20);
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outseq(0x01, regs[SEQ + 1] | 0x20);
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for (i = 2; i < SEQ_C; i++) {
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outseq(i, regs[SEQ + i]);
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}
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outseq(0x0, 0x3);
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// crtc
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// write enable
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val = incrtc(0x11);
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val &= 0x7F;
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outcrtc(0x11, val);
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// crtc setting
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for (i = 0; i < CRT_C; i++) {
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outcrtc(i, regs[CRT + i]);
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}
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// gra
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for (i = 0; i < GRA_C; i++) {
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outgra(i, regs[GRA + i]);
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}
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// att
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for (i = 0; i < ATT_C; i++) {
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outatt(i, regs[ATT + i]);
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}
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outseq(0x01, regs[SEQ + 1] & 0xDF);
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linux_inb(0x3da);
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vgadelay();
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linux_outb(0x20, 0x3c0);
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// misc readback
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vgadelay();
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linux_outb(0x67, 0x3c2);
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}
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extern struct pci_device *vga_dev;
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extern int vga_available;
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extern int novga;
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extern int vesa_mode;
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extern struct vesamode *vesa_mode_head;
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int vga_bios_init(void)
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{
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xf86Int10InfoPtr pInt;
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int screen;
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void *base = 0;
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void *vbiosMem = 0;
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legacyVGARec vga;
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pInt = (xf86Int10InfoPtr) malloc(sizeof(xf86Int10InfoRec));
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//pInt = (xf86Int10InfoPtr) calloc(1,sizeof(xf86Int10InfoRec));
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memset(pInt, 0, sizeof(xf86Int10InfoRec));
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if (!xf86Int10ExecSetup(pInt))
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goto error0;
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pInt->mem = &genericMem;
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pInt->private = (pointer) malloc(sizeof(genericInt10Priv));
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//pInt->private = (pointer) calloc(1,sizeof(genericInt10Priv));
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memset(pInt->private, 0, sizeof(genericInt10Priv));
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pInt->scrnIndex = 0; /* screen */
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base = INTPriv(pInt)->base = malloc(0x100000);
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//base = INTPriv(pInt)->base = 0x80000000+memorysize-0x100000;
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//#if 0
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#if defined(RS690) || defined(RS780E)
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{
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pcitag_t vga_bridge = _pci_make_tag(0, 1, 0);
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unsigned int val;
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/* enable VGA legacy space decode */
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val = _pci_conf_read(vga_bridge, 0x3c);
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val |= 1 << 19;
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_pci_conf_write(vga_bridge, 0x3c, val);
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/* reallocate the prefetchable address */
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#if 0
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//_pci_conf_write(vga_bridge, 0x20, 0x16101600);
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//_pci_conf_write(vga_bridge, 0x24, 0x15f01400);
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printf("\n\nvga_bridge, 0x20=%x,0x24=%x\n\n\n",
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_pci_conf_read(vga_bridge, 0x20),_pci_conf_read(vga_bridge, 0x24));
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_pci_conf_write(vga_bridge, 0x20, 0x12101200);
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_pci_conf_write(vga_bridge, 0x24, 0x11f01000);
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#else
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/* using the old one */
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#endif
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}
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#endif
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/*
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* we need to map video RAM MMIO as some chipsets map mmio
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* registers into this range.
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*/
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INTPriv(pInt)->vRam = (void *)vgaram_base;
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if (!sysMem) {
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sysMem = malloc(BIOS_SIZE);
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setup_system_bios(sysMem);
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}
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INTPriv(pInt)->sysMem = sysMem;
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printf("memorysize=%x,base=%lx,sysMem=%lx,vram=%lx\n", memorysize,
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INTPriv(pInt)->base, sysMem, INTPriv(pInt)->vRam);
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setup_int_vect(pInt);
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set_return_trap(pInt);
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vbiosMem = (char *)base + V_BIOS;
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(void)memset(vbiosMem, 0, 2 * V_BIOS_SIZE);
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{
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struct pci_device *pdev;
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unsigned long romsize = 0;
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unsigned long romaddress = 0;
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unsigned char magic[2];
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unsigned short ppcidata; /* pointer to pci data structure */
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unsigned char pcisig[4]; /* signature of pci data structure */
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unsigned char codetype;
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if (vga_dev != NULL) {
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pdev = vga_dev;
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printk
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("Found VGA device: vendor=0x%04x, device=0x%04x\n",
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PCI_VENDOR(pdev->pa.pa_id),
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PCI_PRODUCT(pdev->pa.pa_id));
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} else
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return -1;
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if (PCI_VENDOR(pdev->pa.pa_id) == 0x102b) {
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printk("skipping matrox cards\n");
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return -1;
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}
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if (PCI_VENDOR(pdev->pa.pa_id) == 0x1002
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&& PCI_PRODUCT(pdev->pa.pa_id) == 0x4750)
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MEM_WW(pInt, 0xc015e, 0x4750);
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romaddress = _pci_conf_read(pdev->pa.pa_tag, 0x30);
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romaddress &= (~1);
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/* enable rom address decode */
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_pci_conf_write(pdev->pa.pa_tag, 0x30, romaddress | 1);
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#if defined(RADEON7000) || defined(RS690) || defined(VESAFB) || defined(RS780E)
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{
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extern unsigned char vgarom[];
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unsigned char *tmp;
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romaddress = (unsigned long)vgarom;
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tmp = (unsigned char *)vgarom;
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// printk("Here after vgarom romaddress:%x\n",tmp[4]);
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printk("vgarom romaddress:0x%x\n",romaddress);
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}
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#endif
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if (romaddress == 0) {
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printk("No rom address assigned,skipped\n");
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return -1;
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}
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#if defined(BONITOEL) && !( defined(RADEON7000) || defined(VESAFB) || defined(RS690) || defined(RS780E))
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romaddress |= 0x10000000;
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#endif
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printk("Rom base addr: %lx\n", romaddress);
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#ifdef LS3_HT
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magic[0] = *(unsigned char *)(romaddress);
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magic[1] = *(unsigned char *)(romaddress + 1);
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#else
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magic[0] = readb(romaddress);
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magic[1] = readb(romaddress + 1);
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#endif
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if (magic[0] == 0x55 && magic[1] == 0xaa) {
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printk("VGA bios found\n");
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/* rom size is stored at offset 2,in 512 byte unit */
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#ifdef LS3_HT
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romsize = (*(unsigned char *)(romaddress + 2)) * 512;
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#else
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romsize = (readb(romaddress + 2)) * 512;
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#endif
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printk("rom size is %ldk\n", romsize / 1024);
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#ifdef LS3_HT
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ppcidata = *(unsigned int *)(romaddress + 0x18);
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printk("PCI data structure at offset %x\n", ppcidata);
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pcisig[0] = *(unsigned char *)(romaddress + ppcidata);
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pcisig[1] = *(unsigned char *)(romaddress + ppcidata + 1);
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pcisig[2] = *(unsigned char *)(romaddress + ppcidata + 2);
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pcisig[3] = *(unsigned char *)(romaddress + ppcidata + 3);
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#else
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ppcidata = readw(romaddress + 0x18);
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printk("PCI data structure at offset %x\n", ppcidata);
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pcisig[0] = readb(romaddress + ppcidata);
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pcisig[1] = readb(romaddress + ppcidata + 1);
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pcisig[2] = readb(romaddress + ppcidata + 2);
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pcisig[3] = readb(romaddress + ppcidata + 3);
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#endif
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if (pcisig[0] != 'P' || pcisig[1] != 'C' ||
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pcisig[2] != 'I' || pcisig[3] != 'R') {
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printk("PCIR expected,read %c%c%c%c\n",
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pcisig[0], pcisig[1], pcisig[2],
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pcisig[3]);
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printk("Invalid pci signature found,give up\n");
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return -1;
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}
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#ifdef LS3_HT
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codetype = *(unsigned char *)(romaddress + ppcidata + 0x14);
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#else
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codetype = readb(romaddress + ppcidata + 0x14);
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#endif
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if (codetype != 0) {
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printk("Not x86 code in rom,give up\n");
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return -1;
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}
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#if defined(RS690) || defined(RS780E) // fixup PCI ID
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//*((volatile unsigned int *)(0xa0000000 | (romaddress + ppcidata + 4))) = _pci_conf_read(pdev->pa.pa_tag, 0x00);
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*((volatile unsigned int *)((romaddress + ppcidata + 4))) = _pci_conf_read(pdev->pa.pa_tag, 0x00);
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#endif
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} else {
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printk("No valid bios found,magic=%x%x\n", magic[0],
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magic[1]);
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return -1;
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}
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pInt->pdev = pdev;
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memcpy(vbiosMem, (char *)(0x00000000 | romaddress),
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V_BIOS_SIZE);
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#if defined(RS780E)
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memcpy(0xc3f00000 , (char *)(0x00000000 | romaddress) , V_BIOS_SIZE);
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//memcpy(0xdff00000 , (char *)(0x00000000 | romaddress) , V_BIOS_SIZE);
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//memcpy(0xc7f00000 , (char *)(0x00000000 | romaddress) , V_BIOS_SIZE);
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#endif
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if (PCI_VENDOR(pdev->pa.pa_id) == 0x1002
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&& PCI_PRODUCT(pdev->pa.pa_id) == 0x4750)
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MEM_WW(pInt, 0xc015e, 0x4750);
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#if defined(RS780E)
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//for test
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MEM_WW(pInt , 0xcac90 , 0x1 | MEM_RW(pInt , 0xcac90));
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#endif
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}
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#if 0
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setregs(regs);
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#else
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pInt->BIOSseg = V_BIOS >> 4;
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pInt->num = 0xe6;
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printf("lock vga\n");
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//LockLegacyVGA(screen, &vga);
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printf("starting bios emu...\n");
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M.x86.debug |= /*DEBUG_STEP_F | DEBUG_DECODE_F | DEBUG_TRACE_F | DEBUG_MEM_TRACE_F */ DEBUG_IO_TRACE_F | DEBUG_DECODE_F;
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//X86EMU_trace_on();
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// printf("end of trace ......................................\n");
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printf("ax=%lx,bx=%lx,cx=%lx,dx=%lx\n", pInt->ax, pInt->bx, pInt->cx, pInt->dx);
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xf86ExecX86int10(pInt);
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printf("just before emu done ax(0x%x)\n", pInt->ax);
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printf("bios emu done\n");
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#if 0
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pInt->num = 0x10;
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pInt->ax = 0x03;
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xf86ExecX86int10(pInt);
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#endif
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//UnlockLegacyVGA(screen, &vga);
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setregs(regs);
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//linux_outb(0x67, 0x3c2);
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#if NMOD_FRAMEBUFFER == 0
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printf("setting text mode...\n");
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//X86EMU_trace_on();
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pInt->BIOSseg = V_BIOS >> 4;
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pInt->num = 0x10;
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pInt->ax = 0x0003;
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xf86ExecX86int10(pInt);
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#else
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//printf("setting fb mode...\n");
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pInt->BIOSseg = V_BIOS >> 4;
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pInt->num = 0x10;
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{
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char *mode;
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mode = getenv("vesa_mode");
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if (mode != 0)
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vesa_mode = strtol(mode, 0, 0);
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else
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vesa_mode = 0x00;
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}
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for(vesa_mode = 0; vesa_mode <= 24; vesa_mode++){
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printk("\n\nvesa_mode : 0x%x\n", vesa_mode);
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pInt->ax = 0x4f02;
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// pInt->bx = 0x4114;
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pInt->bx = (USE_LINEAR_FRAMEBUFFER | vesa_mode_head[vesa_mode].mode);
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printk("ax %x bx %x\n", pInt->ax, pInt->bx);
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xf86ExecX86int10(pInt);
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if (pInt->ax != 0x004f){
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printk("set vesa mode failed,ax=%x mode(0x%x)\n", pInt->ax, pInt->bx);
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}else{
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break;
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}
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}
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#ifdef DEBUG
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pInt->ax = 0x4f01; /* get mode information */
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pInt->cx = 0x4114;
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pInt->di = 0;
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pInt->es = 0;
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xf86ExecX86int10(pInt);
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if (pInt->ax != 0x004f)
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printk("get vesa mode info failed,ax=%x\n", pInt->ax);
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printk("linelength=%x\n", MEM_RW(pInt, pInt->di + 16));
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printk("width=%x\n", MEM_RW(pInt, pInt->di + 18));
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printk("height=%x\n", MEM_RW(pInt, pInt->di + 20));
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printk("depth=%x\n", MEM_RB(pInt, pInt->di + 25));
|
|
printk("pages=%x\n", MEM_RB(pInt, pInt->di + 29));
|
|
printk("base=%x\n", MEM_RL(pInt, pInt->di + 40));
|
|
#endif
|
|
#endif
|
|
|
|
#endif
|
|
|
|
#if 0
|
|
radeon_init_regbase();
|
|
radeon_init_mode();
|
|
radeon_engine_init();
|
|
//radeon_dump_regs();
|
|
#endif
|
|
|
|
free(pInt->private);
|
|
free(pInt);
|
|
free(sysMem);
|
|
free(base);
|
|
return 1;
|
|
error0:
|
|
free(pInt);
|
|
|
|
return -1;
|
|
}
|
|
|
|
Bool MapCurrentInt10(xf86Int10InfoPtr pInt)
|
|
{
|
|
/* nothing to do here */
|
|
return TRUE;
|
|
}
|
|
|
|
#define MMIO_IN8(base, offset) \
|
|
*(volatile CARD8 *)(((CARD8*)(base)) + (offset))
|
|
#define MMIO_IN16(base, offset) \
|
|
*(volatile CARD16 *)(((CARD8*)(base)) + (offset))
|
|
#define MMIO_IN32(base, offset) \
|
|
*(volatile CARD32 *)(((CARD8*)(base)) + (offset))
|
|
#define MMIO_OUT8(base, offset, val) \
|
|
*(volatile CARD8 *)(((CARD8*)(base)) + (offset)) = (val)
|
|
#define MMIO_OUT16(base, offset, val) \
|
|
*(volatile CARD16 *)(((CARD8*)(base)) + (offset)) = (val)
|
|
#define MMIO_OUT32(base, offset, val) \
|
|
*(volatile CARD32 *)(((CARD8*)(base)) + (offset)) = (val)
|
|
|
|
#define OFF(addr) ((addr) & 0xffff)
|
|
#define SYS(addr) ((addr) >= SYS_BIOS)
|
|
#define V_ADDR(addr) \
|
|
(SYS(addr) ? ((char*)INTPriv(pInt)->sysMem) + (addr - SYS_BIOS) \
|
|
: ((char*)(INTPriv(pInt)->base) + addr))
|
|
#define VRAM_ADDR(addr) (addr - V_RAM)
|
|
#define VRAM_BASE (INTPriv(pInt)->vRam)
|
|
|
|
#define VRAM(addr) ((addr >= V_RAM) && (addr < (V_RAM + VRAM_SIZE)))
|
|
#define V_ADDR_RB(addr) \
|
|
(VRAM((addr))) ? MMIO_IN8((CARD8*)VRAM_BASE,VRAM_ADDR((addr))) \
|
|
: *(CARD8*) V_ADDR((addr))
|
|
#define V_ADDR_RW(addr) \
|
|
(VRAM((addr))) ? MMIO_IN16((CARD16*)VRAM_BASE,VRAM_ADDR((addr))) \
|
|
: (*(CARD16*)V_ADDR((addr)))
|
|
#define V_ADDR_RL(addr) \
|
|
(VRAM((addr))) ? MMIO_IN32((CARD32*)VRAM_BASE,VRAM_ADDR((addr))) \
|
|
: (*(CARD32*)V_ADDR((addr)))
|
|
|
|
#define V_ADDR_WB(addr,val) \
|
|
if(VRAM((addr))) { \
|
|
MMIO_OUT8((CARD8*)VRAM_BASE,VRAM_ADDR((addr)),val); \
|
|
} else \
|
|
*(CARD8*) V_ADDR((addr)) = val;
|
|
#define V_ADDR_WW(addr,val) \
|
|
if(VRAM((addr))) \
|
|
MMIO_OUT16((CARD16*)VRAM_BASE,VRAM_ADDR((addr)),val); \
|
|
else \
|
|
*(CARD16*)(V_ADDR((addr))) = val;
|
|
|
|
#define V_ADDR_WL(addr,val) \
|
|
if (VRAM((addr))) \
|
|
MMIO_OUT32((CARD32*)VRAM_BASE,VRAM_ADDR((addr)),val); \
|
|
else \
|
|
*(CARD32*)(V_ADDR((addr))) = val;
|
|
|
|
static CARD8 read_b(xf86Int10InfoPtr pInt, int addr)
|
|
{
|
|
return V_ADDR_RB(addr);
|
|
}
|
|
|
|
static CARD16 read_w(xf86Int10InfoPtr pInt, int addr)
|
|
{
|
|
// return V_ADDR_RW(addr);
|
|
#ifdef DEBUG_READ
|
|
printf("read_w %x %x %x\n", V_ADDR_RB(addr), ((CARD16)(V_ADDR_RB((addr + 1))) << 8),
|
|
(CARD16)(V_ADDR_RB(addr)) | ((CARD16)(V_ADDR_RB(addr + 1)) << 8));
|
|
#endif
|
|
return (CARD16)(V_ADDR_RB(addr)) | ((CARD16)(V_ADDR_RB(addr + 1)) << 8);
|
|
}
|
|
|
|
static CARD32 read_l(xf86Int10InfoPtr pInt, int addr)
|
|
{
|
|
// return V_ADDR_RL(addr);
|
|
return (CARD32)(V_ADDR_RB(addr)) |
|
|
((CARD32)(V_ADDR_RB(addr + 1)) << 8) |
|
|
((CARD32)(V_ADDR_RB(addr + 2)) << 16) | ((CARD32)(V_ADDR_RB(addr + 3)) << 24);
|
|
}
|
|
|
|
static void write_b(xf86Int10InfoPtr pInt, int addr, CARD8 val)
|
|
{
|
|
V_ADDR_WB(addr, (val & 0xff));
|
|
#ifdef DEBUG_WRITE
|
|
if (VRAM(addr) && val)
|
|
printf("%08x wb %x, rd %x\n", addr, val, read_b(pInt, addr));
|
|
#endif
|
|
}
|
|
|
|
static void write_w(xf86Int10InfoPtr pInt, int addr, CARD16 val)
|
|
{
|
|
V_ADDR_WB(addr, (val & 0xff));
|
|
V_ADDR_WB(addr+1, ((val >> 8) & 0xff));
|
|
#ifdef DEBUG_WRITE
|
|
if (VRAM(addr) && val)
|
|
printf("%08x ww %x, rd %x\n", addr, val, read_w(pInt, addr));
|
|
#endif
|
|
}
|
|
|
|
static void write_l(xf86Int10InfoPtr pInt, int addr, CARD32 val)
|
|
{
|
|
V_ADDR_WB(addr, (val & 0xff));
|
|
V_ADDR_WB(addr+1, ((val >> 8) & 0xff));
|
|
V_ADDR_WB(addr+2, ((val >> 16) & 0xff));
|
|
V_ADDR_WB(addr+3, ((val >> 24) & 0xff));
|
|
#ifdef DEBUG_WRITE
|
|
if (VRAM(addr) && val)
|
|
printf("%08x wl %x, rd %x\n", addr, val, read_l(pInt, addr));
|
|
#endif
|
|
}
|
|
|
|
pointer xf86int10Addr(xf86Int10InfoPtr pInt, CARD32 addr)
|
|
{
|
|
return V_ADDR(addr);
|
|
}
|
|
|