1. Disable LPC CTRL/MEM/MMIO-BAR and set them to fix address.
CTRL: 0x10002000~0x10002fff;
MEM: 0x12000000~0x13ffffff;
IO: 0x18000000~0x1801ffff;
As the kernel need also be modified to reserve the low 128KB IO space and skip LPC BAR, so we disable board LPC now.
The GPU emu code is also modified.
2. Fix GPU/DC class code.
3. Disable 3A HT dw_write to support mask write and change the PIX pll default setting.
4. Fix WatchDog control defination.
5. Disable HT freq soft configure to fix possible HT link fail. And add check of HT pll lock.
Change-Id: I1ac3eaacc1fcda52b8ae1a0dbbdc0306833da7dc
Chen Xinke
ab9c1a4be0