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1115 lines
23 KiB
1115 lines
23 KiB
/* $Id: startz.S,v 1.1.1.1 2006/09/14 01:59:08 root Exp $ */
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/*
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* Copyright (c) 2001 Opsycon AB (www.opsycon.se)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Opsycon AB, Sweden.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#ifndef _KERNEL
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#define _KERNEL
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#endif
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#include <asm.h>
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#include <regnum.h>
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#include <cpu.h>
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#include <pte.h>
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#include "pmon/dev/ns16550.h"
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#include "target/i82371eb.h"
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#include "target/prid.h"
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#include "target/sbd.h"
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#include "target/bonito.h"
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#include "target/i8254.h"
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#include "target/pc97307.h"
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#include "target/isapnpreg.h"
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#define DEBUG_LOCORE
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#undef DEBUG_DIMM_SPD
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#ifdef DEBUG_LOCORE
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#define TTYDBG(x) \
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.rdata;98: .asciz x; .text; la a0, 98b; bal stringserial; nop
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#else
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#define TTYDBG(x)
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#endif
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#define PRINTSTR(x) \
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.rdata;98: .asciz x; .text; la a0, 98b; bal stringserial; nop
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#define CONFIG_CACHE_64K_4WAY 1
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#define tmpsize s1
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#define msize s2
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#define sdShape s3
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#define bonito s4
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#define dbg s5
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#define sdCfg s6
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#define CFG_IB 0x00000020
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#define CFG_DB 0x00000010
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#define CFG_C_WBACK 3
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#define CFG_BE 0x00008000
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#define CFG_EPMASK 0x0f000000
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#define CFG_EPD 0x00000000
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#define CFG_EM_R4K 0x00000000
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#define CFG_EMMASK 0x00c00000
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#define CFG_AD 0x00800000
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#define CP0_CONFIG $16
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#define CP0_TAGLO $28
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#define CP0_TAGHI $29
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#define DDR100 0x1d441091
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/*
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#define DDR100 0x0c011091*/
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#define DDR266 0x0410435e
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#define DDR300 0x041453df
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/*
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* Register usage:
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*
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* s0 link versus load offset, used to relocate absolute adresses.
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* s1 free
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* s2 memory size.
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* s3 sdShape.
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* s4 Bonito base address.
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* s5 dbg.
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* s6 sdCfg.
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* s7 rasave.
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* s8 L3 Cache size.
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*/
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.set noreorder
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.globl _start
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.globl start
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.globl __main
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_start:
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start:
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.globl stack
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stack = start - 0x4000 /* Place PMON stack below PMON start in RAM */
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/* NOTE!! Not more that 16 instructions here!!! Right now it's FULL! */
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mtc0 zero, COP_0_STATUS_REG
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mtc0 zero, COP_0_CAUSE_REG
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li t0, SR_BOOT_EXC_VEC /* Exception to Boostrap Location */
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mtc0 t0, COP_0_STATUS_REG
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la sp, stack
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la gp, _gp
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bal uncached /* Switch to uncached address space */
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nop
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bal locate /* Get current execute address */
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nop
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uncached:
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or ra, UNCACHED_MEMORY_ADDR
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j ra
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nop
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/*
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* Exception vectors here for rom, before we are up and running. Catch
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* whatever comes up before we have a fully fledged exception handler.
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*/
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.align 8
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nop
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.align 8
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.word read
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.word write
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.word open
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.word close
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.word nullfunction
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.word printf
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.word vsprintf
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.word nullfunction
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.word nullfunction
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.word getenv
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.word nullfunction
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.word nullfunction
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.word nullfunction
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.word nullfunction
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/*
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* We get here from executing a bal to get the PC value of the current execute
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* location into ra. Check to see if we run from ROM or if this is ramloaded.
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*/
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locate:
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la s0,start
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subu s0,ra,s0
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and s0,0xffff0000
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li t0,SR_BOOT_EXC_VEC
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mtc0 t0,COP_0_STATUS_REG
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mtc0 zero,COP_0_CAUSE_REG
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.set noreorder
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li bonito,PHYS_TO_UNCACHED(BONITO_REG_BASE)
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#define MOD_MASK 0x00000003
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#define MOD_B 0x00000000 /* byte "modifier" */
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#define MOD_H 0x00000001 /* halfword "modifier" */
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#define MOD_W 0x00000002 /* word "modifier" */
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#if __mips64
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# define MOD_D 0x00000003 /* doubleword "modifier" */
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#endif
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#define OP_MASK 0x000000fc
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#define OP_EXIT 0x00000000 /* exit (status) */
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#define OP_DELAY 0x00000008 /* delay (cycles) */
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#define OP_RD 0x00000010 /* read (addr) */
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#define OP_WR 0x00000014 /* write (addr, val) */
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#define OP_RMW 0x00000018 /* read-modify-write (addr, and, or) */
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#define OP_WAIT 0x00000020 /* wait (addr, mask, value) */
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#define WR_INIT(mod,addr,val) \
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.word OP_WR|mod,PHYS_TO_UNCACHED(addr);\
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.word (val),0
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#define RD_INIT(mod,addr) \
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.word OP_RD|mod,PHYS_TO_UNCACHED(addr);\
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.word 0,0
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#define RMW_INIT(mod,addr,and,or) \
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.word OP_RMW|mod,PHYS_TO_UNCACHED(addr);\
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.word (and),(or)
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#define WAIT_INIT(mod,addr,and,or) \
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.word OP_WAIT|mod,PHYS_TO_UNCACHED(addr);\
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.word (mask),(val)
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#define DELAY_INIT(cycles) \
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.word OP_DELAY,(cycles);\
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.word 0,0
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#define EXIT_INIT(status) \
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.word OP_EXIT,(status);\
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.word 0,0
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#define BONITO_INIT(r,v) WR_INIT(MOD_W,BONITO_BASE+/**/r,v)
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#define BONITO_BIS(r,b) RMW_INIT(MOD_W,BONITO_BASE+(r),~0,b)
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#define BONITO_BIC(r,b) RMW_INIT(MOD_W,BONITO_BASE+(r),~(b),0)
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#define BONITO_RMW(r,c,s) RMW_INIT(MOD_W,BONITO_BASE+(r),~(c),s)
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#define CFGADDR(idsel,function,reg) ((1<<(11+(idsel)))+((function)<<8)+(reg))
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#define _ISABWR_INIT(mod,function,isabreg,val) \
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WR_INIT(MOD_W,BONITO_BASE+BONITO_PCIMAP_CFG,CFGADDR(PCI_IDSEL_VIA686B,function,isabreg)>>16) ; \
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RD_INIT(MOD_W,BONITO_BASE+BONITO_PCIMAP_CFG) ; \
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WR_INIT(mod,PCI_CFG_SPACE+(CFGADDR(PCI_IDSEL_VIA686B,function,isabreg)&0xffff),val)
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#define _ISABRD_INIT(mod,function,isabreg) \
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WR_INIT(MOD_W,BONITO_BASE+BONITO_PCIMAP_CFG,CFGADDR(PCI_IDSEL_VIA686B,function,isabreg)>>16) ; \
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RD_INIT(MOD_W,BONITO_BASE+BONITO_PCIMAP_CFG) ; \
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RD_INIT(mod,PCI_CFG_SPACE+(CFGADDR(PCI_IDSEL_VIA686B,function,isabreg)&0xffff))
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#define _ISAWR_INIT(isareg,val) \
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WR_INIT(MOD_B,PCI_IO_SPACE+(isareg),val)
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#define _ISARD_INIT(isareg) \
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RD_INIT(MOD_B,PCI_IO_SPACE+(isareg))
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#define ISABBWR_INIT(function,isabreg,val) \
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_ISABWR_INIT(MOD_B,function,(isabreg),val)
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#define ISABHWR_INIT(function,isabreg,val) \
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_ISABWR_INIT(MOD_H,function,(isabreg),val)
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#define ISABWWR_INIT(function,isabreg,val) \
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_ISABWR_INIT(MOD_W,function,isabreg,val)
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#define ISAWR_INIT(isareg,val) \
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_ISAWR_INIT(isareg,val)
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#define ISARD_INIT(isareg) \
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_ISARD_INIT(isareg)
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bal 1f
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nop
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/*
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* In certain situations it is possible for the Bonito ASIC
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* to come up with the PCI registers uninitialised, so do them here
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*/
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#define PCI_CLASS_BRIDGE 0x06
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#define PCI_CLASS_SHIFT 24
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#define PCI_SUBCLASS_BRIDGE_HOST 0x00
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#define PCI_SUBCLASS_SHIFT 16
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#define PCI_COMMAND_IO_ENABLE 0x00000001
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#define PCI_COMMAND_MEM_ENABLE 0x00000002
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#define PCI_COMMAND_MASTER_ENABLE 0x00000004
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#define PCI_COMMAND_STATUS_REG 0x04
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#define PCI_MAP_IO 0X00000001
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#define PCI_DEV_VIA686B 17
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#define PCI_CFG_SPACE BONITO_PCICFG_BASE
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#define Init_Op 0
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#define Init_A0 4
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#define Init_A1 8
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#define Init_A2 12
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#define Init_Size 16
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1: move a0,ra
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.done:
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/* plj. initialize southbridge */
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li a0,CFGADDR(PCI_DEV_VIA686B,3,PCI_COMMAND_STATUS_REG)
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li a1,PHYS_TO_UNCACHED(PCI_CFG_SPACE)
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and a2,a0,0xffff
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or a1,a2
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srl a0,16
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li a2,BONITO_BASE+BONITO_PCIMAP_CFG
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sw a0,BONITO_PCIMAP_CFG(bonito)
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lw zero,BONITO_PCIMAP_CFG(bonito)
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lw t0,(a1)
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ori t0, 0x02|0x04
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sw a0,BONITO_PCIMAP_CFG(bonito)
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lw zero,BONITO_PCIMAP_CFG(bonito)
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sw t0,(a1)
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/* Initialise other low-level I/O devices */
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bal superio_init
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nop
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bal initserial
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nop
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PRINTSTR("\r\nPMON2000 MIPS Initializing. Standby...\r\n")
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PRINTSTR("ERRORPC=")
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mfc0 a0, COP_0_ERROR_PC
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bal hexserial
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nop
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PRINTSTR(" CONFIG=")
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mfc0 a0, COP_0_CONFIG
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bal hexserial
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nop
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PRINTSTR("\r\n")
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PRINTSTR(" PRID=")
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mfc0 a0, COP_0_PRID
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bal hexserial
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nop
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PRINTSTR("\r\n")
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#if 0 /* zhb cpu*/
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li msize,0x10000000
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#li sdCfg,0x0544e091
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#li sdCfg,0x1d44e091
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li sdCfg,0x3d500081 #~133MHz
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# li sdCfg,0x3d540081 #~166MHz
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li t0, 0xbff00008
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sd sdCfg, 0(t0)
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#### gx 2006-03-17: mode ####
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#li t1,0x20
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li t1,0x28
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li t0, 0xbff00000
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sw t1,0(t0)
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nop
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li t1,0x0
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li t0, 0xbff00000
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sw t1,0x30(t0)
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nop
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/*
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lui t0, 0xbff0
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lui t1, 0x2000
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dsll t1, t1, 8
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sd t1, 0x20(t0)
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lui t1, 0x1000
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sd t1, 0x28(t0)
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*/
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#endif
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#if 1//def DBGSBD
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PRINTSTR("sdcfg=");
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move a0,sdCfg
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bal hexserial
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nop
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PRINTSTR("\r\n");
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PRINTSTR("msize=");
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move a0,msize
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bal hexserial
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nop
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PRINTSTR("\r\n")
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#endif
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skipdimm:
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li t1,0 # accumulate pcimembasecfg settings
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/* set bar0 mask and translation to point to SDRAM */
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sub t0,msize,1
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not t0
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srl t0,BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE0_MASK_SHIFT
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and t0,BONITO_PCIMEMBASECFG_MEMBASE0_MASK
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or t1,t0
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li t0,0x00000000
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srl t0,BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE0_TRANS_SHIFT
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and t0,BONITO_PCIMEMBASECFG_MEMBASE0_TRANS
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or t1,t0
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or t1,BONITO_PCIMEMBASECFG_MEMBASE0_CACHED
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/* set bar1 to minimum size to conserve PCI space */
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li t0, ~0
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srl t0,BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE1_MASK_SHIFT
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and t0,BONITO_PCIMEMBASECFG_MEMBASE1_MASK
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or t1,t0
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li t0,0x00000000
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srl t0,BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE1_TRANS_SHIFT
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and t0,BONITO_PCIMEMBASECFG_MEMBASE1_TRANS
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or t1,t0
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or t1,BONITO_PCIMEMBASECFG_MEMBASE1_CACHED
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sw t1,BONITO_PCIMEMBASECFG(bonito)
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/* enable configuration cycles now */
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lw t0,BONITO_BONPONCFG(bonito)
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and t0,~BONITO_BONPONCFG_CONFIG_DIS
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sw t0,BONITO_BONPONCFG(bonito)
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PRINTSTR("Init SDRAM Done!\r\n");
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/*
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* Reset and initialize caches to a known state.
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*/
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#define IndexStoreTagI 0x08
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#define IndexStoreTagD 0x09
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#define IndexStoreTagS 0x0b
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#define IndexStoreTagT 0x0a
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#define FillI 0x14
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/*
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* RM7000 config register bits.
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*/
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#define CF_7_SE (1 << 3) /* Secondary cache enable */
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#define CF_7_SC (1 << 31) /* Secondary cache not present */
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#define CF_7_TE (1 << 12) /* Tertiary cache enable */
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#define CF_7_TC (1 << 17) /* Tertiary cache not present */
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#define CF_7_TS (3 << 20) /* Tertiary cache size */
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#define CF_7_TS_AL 20 /* Shift to align */
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#define NOP8 nop;nop;nop;nop;nop;nop;nop;nop
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do_caches:
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TTYDBG("Sizing caches...\r\n");
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mfc0 t3, COP_0_CONFIG /* t3 = original config */
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and t3, 0xffffeff0 /* Make sure coherency is OK */
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and t3, ~(CF_7_TE|CF_7_SE|CF_7_TC|CF_7_SC) /* disable L2/L3 cache */
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mtc0 t3, COP_0_CONFIG
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li t2, 4096
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srl t1, t3, 9
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and t1, 3
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sllv s3, t2, t1 /* s3 = I cache size */
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#ifdef CONFIG_CACHE_64K_4WAY
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sll s3,2
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#endif
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and t1, t3, 0x20
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srl t1, t1, 1
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addu s4, t1, 16 /* s4 = I cache line size */
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srl t1, t3, 6
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and t1, 3
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sllv s5, t2, t1 /* s5 = D cache size */
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#ifdef CONFIG_CACHE_64K_4WAY
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sll s5,2
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#endif
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and t1, t3, 0x10
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addu s6, t1, 16 /* s6 = D cache line size */
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TTYDBG("Init caches...\r\n")
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li s7, 0 /* no L2 cache */
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li s8, 0 /* no L3 cache */
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#if 0
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mfc0 a0, COP_0_PRID
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li a1, 0x6301
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bne a0,a1,1f
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nop
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#endif
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TTYDBG("godson2 caches found\r\n")
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bal godson2_cache_init
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nop
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#ifdef DEBUG_LOCORE
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TTYDBG("Init caches done, cfg = ")
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mfc0 a0, COP_0_CONFIG
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bal hexserial
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nop
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TTYDBG("\r\n\r\n")
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#endif
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/* zhb */
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#if 0
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/* li t0, 0 */
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/* li t1, 0x90000 */
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/*1: addiu t0, 1 */
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/* bne t0, t1, 1b */
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nop
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TTYDBG("Testing memory...\r\n")
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li t7, 10
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tmem:
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li t0, 0xa0000000+1*1024*1024
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li t1, 0xa0000000
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li t2, 0xffffffff
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|
1:
|
|
sw t2, 0(t1)
|
|
lw t3, 0(t1)
|
|
bne t3, t2, 1f
|
|
nop
|
|
not t2
|
|
sw t2, 0(t1)
|
|
lw t3, 0(t1)
|
|
bne t3, t2, 1f
|
|
nop
|
|
not t2
|
|
subu t2, 1
|
|
addu t1, 4
|
|
beq t1, t0, 2f
|
|
nop
|
|
and t4, t1, 0x000fffff
|
|
bnez t4, skipdot
|
|
li a0, '.'
|
|
bal tgt_putchar
|
|
nop
|
|
skipdot:
|
|
b 1b
|
|
nop
|
|
1:
|
|
TTYDBG("Memory test failed at ");
|
|
move a0, t1
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\nWrite=");
|
|
move a0, t2
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\nRead=");
|
|
move a0, t3
|
|
bal hexserial
|
|
nop
|
|
1:
|
|
b 1b
|
|
nop
|
|
2:
|
|
TTYDBG("Testing ok...\r\n");
|
|
sub t7,1
|
|
beqz t7, 1f
|
|
nop
|
|
b tmem
|
|
nop
|
|
1:
|
|
b 1b
|
|
nop
|
|
#endif
|
|
|
|
/* Clear BSS */
|
|
la a0, _edata
|
|
la a2, _end
|
|
2: sw zero, 0(a0)
|
|
bne a2, a0, 2b
|
|
addu a0, 4
|
|
|
|
TTYDBG("Clear PMON BBS done.\r\n")
|
|
/* zhb */
|
|
#if 0
|
|
zhb:
|
|
TTYDBG("Testing...\r\n")
|
|
la a0, start
|
|
li a1, 0xbfc00000
|
|
la a2, _edata
|
|
or a0, 0xa0000000
|
|
or a2, 0xa0000000
|
|
/* subu s6, a2, a0*/
|
|
/* srl s6, s6, 2*/
|
|
|
|
move t0, a0
|
|
move t1, a1
|
|
move t2, a2
|
|
/* copy text section */
|
|
|
|
1: lw t4, 0(t1)
|
|
nop
|
|
lw t5, 0(t0)
|
|
addu t0, 4
|
|
addu t1, 4
|
|
beq t4, t5, 2f
|
|
nop
|
|
move a0, t0
|
|
subu a0, 4
|
|
bal hexserial
|
|
nop
|
|
TTYDBG (" ")
|
|
move a0, t4
|
|
bal hexserial
|
|
nop
|
|
TTYDBG (" ")
|
|
move a0, t5
|
|
bal hexserial
|
|
nop
|
|
TTYDBG ("\r\n")
|
|
2: bne t2, t0, 1b
|
|
nop
|
|
TTYDBG ("test ok!\r\n")
|
|
/*
|
|
3: beqz zero, 3b
|
|
nop
|
|
*/
|
|
#endif
|
|
|
|
|
|
#if 0
|
|
mfc0 a0,COP_0_CONFIG
|
|
and a0,a0,0xfffffff8
|
|
or a0,a0,0x3
|
|
mtc0 a0,COP_0_CONFIG
|
|
#endif
|
|
|
|
li a0, 4096*1024
|
|
sw a0, CpuTertiaryCacheSize /* Set L3 cache size */
|
|
move a0,msize
|
|
srl a0,20
|
|
#if 1
|
|
li a0,256
|
|
#endif
|
|
la v0, initmips
|
|
jalr v0
|
|
nop
|
|
stuck:
|
|
#ifdef DEBUG_LOCORE
|
|
TTYDBG("Dumping GT64240 setup.\r\n")
|
|
TTYDBG("offset----data------------------------.\r\n")
|
|
li s3, 0
|
|
1:
|
|
move a0, s3
|
|
bal hexserial
|
|
nop
|
|
TTYDBG(": ")
|
|
2:
|
|
add a0, s3, bonito
|
|
lw a0, 0(a0)
|
|
bal hexserial
|
|
addiu s3, 4
|
|
TTYDBG(" ")
|
|
li a0, 0xfff
|
|
and a0, s3
|
|
beqz a0, 3f
|
|
li a0, 0x01f
|
|
and a0, s3
|
|
bnez a0, 2b
|
|
TTYDBG("\r\n")
|
|
b 1b
|
|
nop
|
|
3:
|
|
b 3b
|
|
nop
|
|
|
|
#else
|
|
b stuck
|
|
nop
|
|
#endif
|
|
/*
|
|
* Clear the TLB. Normally called from start.S.
|
|
*/
|
|
#if __mips64
|
|
#define MTC0 dmtc0
|
|
#else
|
|
#define MTC0 mtc0
|
|
#endif
|
|
LEAF(CPU_TLBClear)
|
|
li a3, 0 # First TLB index.
|
|
|
|
li a2, PG_SIZE_4K
|
|
MTC0 a2, COP_0_TLB_PG_MASK # Whatever...
|
|
|
|
1:
|
|
MTC0 zero, COP_0_TLB_HI # Clear entry high.
|
|
MTC0 zero, COP_0_TLB_LO0 # Clear entry low0.
|
|
MTC0 zero, COP_0_TLB_LO1 # Clear entry low1.
|
|
|
|
mtc0 a3, COP_0_TLB_INDEX # Set the index.
|
|
addiu a3, 1
|
|
li a2, 64
|
|
nop
|
|
nop
|
|
tlbwi # Write the TLB
|
|
|
|
bne a3, a2, 1b
|
|
nop
|
|
|
|
jr ra
|
|
nop
|
|
END(CPU_TLBClear)
|
|
|
|
/*
|
|
* Set up the TLB. Normally called from start.S.
|
|
*/
|
|
LEAF(CPU_TLBInit)
|
|
li a3, 0 # First TLB index.
|
|
|
|
li a2, PG_SIZE_16M
|
|
MTC0 a2, COP_0_TLB_PG_MASK # All pages are 16Mb.
|
|
|
|
1:
|
|
and a2, a0, PG_SVPN
|
|
MTC0 a2, COP_0_TLB_HI # Set up entry high.
|
|
|
|
move a2, a0
|
|
srl a2, a0, PG_SHIFT
|
|
and a2, a2, PG_FRAME
|
|
ori a2, PG_IOPAGE
|
|
MTC0 a2, COP_0_TLB_LO0 # Set up entry low0.
|
|
addu a2, (0x01000000 >> PG_SHIFT)
|
|
MTC0 a2, COP_0_TLB_LO1 # Set up entry low1.
|
|
|
|
mtc0 a3, COP_0_TLB_INDEX # Set the index.
|
|
addiu a3, 1
|
|
li a2, 0x02000000
|
|
subu a1, a2
|
|
nop
|
|
tlbwi # Write the TLB
|
|
|
|
bgtz a1, 1b
|
|
addu a0, a2 # Step address 32Mb.
|
|
|
|
jr ra
|
|
nop
|
|
END(CPU_TLBInit)
|
|
|
|
/*
|
|
* Simple character printing routine used before full initialization
|
|
*/
|
|
#if 0
|
|
#define TXWAIT 0x100000
|
|
LEAF(tgt_putchar)
|
|
/* blocking transmit, with timeout */
|
|
li t0,TXWAIT # timeout
|
|
1: lbu t1,PHYS_TO_UNCACHED(0x1fd002fd) # get LSR
|
|
and t1,0x20 # tx ready?
|
|
bnez t1,1f # yup - go and write
|
|
nop
|
|
subu t0,1 # continue until timeout
|
|
bnez t0,1b
|
|
nop
|
|
1: sb a0,PHYS_TO_UNCACHED(0x1fd002f8) # write data
|
|
li t0,TXWAIT # timeout
|
|
1: lbu t1,PHYS_TO_UNCACHED(0x1fd003fd) # get LSR
|
|
and t1,0x20 # tx ready?
|
|
bnez t1,1f # yup - go and write
|
|
nop
|
|
subu t0,1 # continue until timeout
|
|
bnez t0,1b
|
|
nop
|
|
1: sb a0,PHYS_TO_UNCACHED(0x1fd003f8) # write data
|
|
j ra
|
|
nop
|
|
END(tgt_putchar)
|
|
#endif
|
|
|
|
LEAF(stringserial)
|
|
move a2, ra
|
|
addu a1, a0, s0
|
|
lbu a0, 0(a1)
|
|
1:
|
|
beqz a0, 2f
|
|
nop
|
|
bal tgt_putchar
|
|
addiu a1, 1
|
|
b 1b
|
|
lbu a0, 0(a1)
|
|
|
|
2:
|
|
j a2
|
|
nop
|
|
END(stringserial)
|
|
LEAF(outstring)
|
|
move a2, ra
|
|
move a1, a0
|
|
lbu a0, 0(a1)
|
|
1:
|
|
beqz a0, 2f
|
|
nop
|
|
bal tgt_putchar
|
|
addiu a1, 1
|
|
b 1b
|
|
lbu a0, 0(a1)
|
|
|
|
2:
|
|
j a2
|
|
nop
|
|
END(outstring)
|
|
LEAF(hexserial)
|
|
move a2, ra
|
|
move a1, a0
|
|
li a3, 7
|
|
1:
|
|
rol a0, a1, 4
|
|
move a1, a0
|
|
and a0, 0xf
|
|
la v0, hexchar
|
|
addu v0, s0
|
|
addu v0, a0
|
|
bal tgt_putchar
|
|
lbu a0, 0(v0)
|
|
|
|
bnez a3, 1b
|
|
addu a3, -1
|
|
|
|
j a2
|
|
nop
|
|
END(hexserial)
|
|
LEAF(tgt_putchar)
|
|
# la v0, COM1_BASE_ADDR
|
|
la v0, COM3_BASE_ADDR
|
|
1:
|
|
lbu v1, NSREG(NS16550_LSR)(v0)
|
|
and v1, LSR_TXRDY
|
|
beqz v1, 1b
|
|
nop
|
|
|
|
sb a0, NSREG(NS16550_DATA)(v0)
|
|
|
|
move v1, v0
|
|
la v0, COM3_BASE_ADDR
|
|
bne v0, v1, 1b
|
|
nop
|
|
|
|
j ra
|
|
nop
|
|
END(tgt_putchar)
|
|
/* baud rate definitions, matching include/termios.h */
|
|
#define B0 0
|
|
#define B50 50
|
|
#define B75 75
|
|
#define B110 110
|
|
#define B134 134
|
|
#define B150 150
|
|
#define B200 200
|
|
#define B300 300
|
|
#define B600 600
|
|
#define B1200 1200
|
|
#define B1800 1800
|
|
#define B2400 2400
|
|
#define B4800 4800
|
|
#define B9600 9600
|
|
#define B19200 19200
|
|
#define B38400 38400
|
|
#define B57600 57600
|
|
#define B115200 115200
|
|
|
|
LEAF(initserial)
|
|
# la v0, COM1_BASE_ADDR
|
|
la v0, COM3_BASE_ADDR
|
|
1:
|
|
li v1, FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_4
|
|
sb v1, NSREG(NS16550_FIFO)(v0)
|
|
li v1, CFCR_DLAB
|
|
sb v1, NSREG(NS16550_CFCR)(v0)
|
|
li v1, NS16550HZ/(16*CONS_BAUD)
|
|
sb v1, NSREG(NS16550_DATA)(v0)
|
|
srl v1, 8
|
|
sb v1, NSREG(NS16550_IER)(v0)
|
|
li v1, CFCR_8BITS
|
|
sb v1, NSREG(NS16550_CFCR)(v0)
|
|
li v1, MCR_DTR|MCR_RTS
|
|
sb v1, NSREG(NS16550_MCR)(v0)
|
|
li v1, 0x0
|
|
sb v1, NSREG(NS16550_IER)(v0)
|
|
|
|
move v1, v0
|
|
la v0, COM3_BASE_ADDR
|
|
bne v0, v1, 1b
|
|
nop
|
|
|
|
j ra
|
|
nop
|
|
END(initserial)
|
|
|
|
|
|
LEAF(i2cdump)
|
|
jr t4
|
|
nop
|
|
END(i2cdump)
|
|
|
|
|
|
|
|
LEAF(i2cread)
|
|
li v0,-1
|
|
j ra
|
|
nop
|
|
END(i2cread)
|
|
|
|
__main:
|
|
j ra
|
|
nop
|
|
|
|
|
|
.rdata
|
|
hexchar:
|
|
.ascii "0123456789abcdef"
|
|
|
|
.text
|
|
.align 2
|
|
/*
|
|
* I2C Functions used in early startup code to get SPD info from
|
|
* SDRAM modules. This code must be entirely PIC and RAM independent.
|
|
*/
|
|
|
|
/* Delay macro */
|
|
#define DELAY(count) \
|
|
li v0, count; \
|
|
99: \
|
|
bnz vo, 99b;\
|
|
addiu v0, -1
|
|
|
|
|
|
#define I2C_INT_ENABLE 0x80
|
|
#define I2C_ENABLE 0x40
|
|
#define I2C_ACK 0x04
|
|
#define I2C_INT_FLAG 0x08
|
|
#define I2C_STOP_BIT 0x10
|
|
#define I2C_START_BIT 0x20
|
|
|
|
#define I2C_AMOD_RD 0x01
|
|
|
|
#define BUS_ERROR 0x00
|
|
#define START_CONDITION_TRA 0x08
|
|
#define RSTART_CONDITION_TRA 0x10
|
|
#define ADDR_AND_WRITE_BIT_TRA_ACK_REC 0x18
|
|
#define ADDR_AND_READ_BIT_TRA_ACK_REC 0x40
|
|
#define SLAVE_REC_WRITE_DATA_ACK_TRA 0x28
|
|
#define MAS_REC_READ_DATA_ACK_NOT_TRA 0x58
|
|
|
|
#define Index_Store_Tag_D 0x05
|
|
#define Index_Invalidate_I 0x00
|
|
#define Index_Writeback_Inv_D 0x01
|
|
#define Index_Store_Tag_S 0x0b
|
|
#define Index_Writeback_Inv_S 0x03
|
|
|
|
LEAF(nullfunction)
|
|
jr ra
|
|
nop
|
|
END(nullfunction)
|
|
|
|
LEAF(godson2_cache_init)
|
|
####part 2####
|
|
cache_detect_2way:
|
|
mfc0 t4, CP0_CONFIG
|
|
andi t5, t4, 0x0e00
|
|
srl t5, t5, 9
|
|
andi t6, t4, 0x01c0
|
|
srl t6, t6, 6
|
|
addiu t6, t6, 11
|
|
addiu t5, t5, 11
|
|
addiu t4, $0, 1
|
|
sllv t6, t4, t6
|
|
srl t6,1
|
|
sllv t5, t4, t5
|
|
srl t5,1
|
|
addiu t7, $0, 2
|
|
####part 3####
|
|
lui a0, 0x8000
|
|
addu a1, $0, t5
|
|
addu a2, $0, t6
|
|
cache_init_d2way:
|
|
#a0=0x80000000, a1=icache_size, a2=dcache_size
|
|
#a3, v0 and v1 used as local registers
|
|
mtc0 $0, CP0_TAGHI
|
|
addu v0, $0, a0
|
|
addu v1, a0, a2
|
|
1: slt a3, v0, v1
|
|
beq a3, $0, 1f
|
|
nop
|
|
mtc0 $0, CP0_TAGLO
|
|
cache Index_Store_Tag_D, 0x0(v0)
|
|
mtc0 $0, CP0_TAGLO
|
|
cache Index_Store_Tag_D, 0x1(v0)
|
|
mtc0 $0, CP0_TAGLO
|
|
cache Index_Store_Tag_D, 0x2(v0)
|
|
mtc0 $0, CP0_TAGLO
|
|
cache Index_Store_Tag_D, 0x3(v0)
|
|
beq $0, $0, 1b
|
|
addiu v0, v0, 0x20
|
|
|
|
#if 1
|
|
1:
|
|
cache_init_l24way:
|
|
mtc0 $0, CP0_TAGHI
|
|
addu v0, $0, a0
|
|
addu v1, a0, 128*1024
|
|
1: slt a3, v0, v1
|
|
beq a3, $0, 1f
|
|
nop
|
|
mtc0 $0, CP0_TAGLO
|
|
cache Index_Store_Tag_S, 0x0(v0)
|
|
mtc0 $0, CP0_TAGLO
|
|
cache Index_Store_Tag_S, 0x1(v0)
|
|
mtc0 $0, CP0_TAGLO
|
|
cache Index_Store_Tag_S, 0x2(v0)
|
|
mtc0 $0, CP0_TAGLO
|
|
cache Index_Store_Tag_S, 0x3(v0)
|
|
beq $0, $0, 1b
|
|
addiu v0, v0, 0x20
|
|
|
|
|
|
1:
|
|
cache_flush_4way:
|
|
addu v0, $0, a0
|
|
addu v1, a0, 128*1024
|
|
1: slt a3, v0, v1
|
|
beq a3, $0, 1f
|
|
nop
|
|
cache Index_Writeback_Inv_S, 0x0(v0)
|
|
cache Index_Writeback_Inv_S, 0x1(v0)
|
|
cache Index_Writeback_Inv_S, 0x2(v0)
|
|
cache Index_Writeback_Inv_S, 0x3(v0)
|
|
beq $0, $0, 1b
|
|
addiu v0, v0, 0x20
|
|
# endif
|
|
|
|
1:
|
|
cache_flush_i2way:
|
|
addu v0, $0, a0
|
|
addu v1, a0, a1
|
|
1: slt a3, v0, v1
|
|
beq a3, $0, 1f
|
|
nop
|
|
cache Index_Invalidate_I, 0x0(v0)
|
|
# cache Index_Invalidate_I, 0x1(v0)
|
|
# cache Index_Invalidate_I, 0x2(v0)
|
|
# cache Index_Invalidate_I, 0x3(v0)
|
|
beq $0, $0, 1b
|
|
addiu v0, v0, 0x20
|
|
1:
|
|
cache_flush_d2way:
|
|
addu v0, $0, a0
|
|
addu v1, a0, a2
|
|
1: slt a3, v0, v1
|
|
beq a3, $0, 1f
|
|
nop
|
|
cache Index_Writeback_Inv_D, 0x0(v0)
|
|
cache Index_Writeback_Inv_D, 0x1(v0)
|
|
cache Index_Writeback_Inv_D, 0x2(v0)
|
|
cache Index_Writeback_Inv_D, 0x3(v0)
|
|
beq $0, $0, 1b
|
|
addiu v0, v0, 0x20
|
|
1:
|
|
cache_init_finish:
|
|
nop
|
|
jr ra
|
|
nop
|
|
|
|
cache_init_panic:
|
|
TTYDBG("cache init panic\r\n");
|
|
1: b 1b
|
|
nop
|
|
.end godson2_cache_init
|
|
|
|
#define PCICONF_WRITEB(dev,func,reg,data) \
|
|
li a0,CFGADDR(dev,func,reg); \
|
|
li a1,PHYS_TO_UNCACHED(PCI_CFG_SPACE); \
|
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and a2,a0,0xffff; \
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or a1,a2; \
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srl a0,16; \
|
|
li a2,BONITO_BASE+BONITO_PCIMAP_CFG; \
|
|
sw a0,BONITO_PCIMAP_CFG(bonito); \
|
|
lw zero,BONITO_PCIMAP_CFG(bonito); \
|
|
or a0,zero,data; \
|
|
sb a0,(a1);
|
|
|
|
#define PCICONF_WRITEW(dev,func,reg,data) \
|
|
li a0,CFGADDR(dev,func,reg); \
|
|
li a1,PHYS_TO_UNCACHED(PCI_CFG_SPACE); \
|
|
and a2,t0,0xffff; \
|
|
or a1,a2; \
|
|
srl a0,16; \
|
|
li a2,BONITO_BASE+BONITO_PCIMAP_CFG; \
|
|
sw a0,BONITO_PCIMAP_CFG(bonito); \
|
|
lw zero,BONITO_PCIMAP_CFG(bonito); \
|
|
or a0,zero,data; \
|
|
sw a0,(a1);
|
|
#define PCICONF_ORB(dev,func,reg,data) \
|
|
li a0,CFGADDR(dev,func,reg); \
|
|
li a1,PHYS_TO_UNCACHED(PCI_CFG_SPACE); \
|
|
and a2,a0,0xffff; \
|
|
or a1,a2; \
|
|
srl a0,16; \
|
|
li a2,BONITO_BASE+BONITO_PCIMAP_CFG; \
|
|
sw a0,BONITO_PCIMAP_CFG(bonito); \
|
|
lw zero,BONITO_PCIMAP_CFG(bonito); \
|
|
lbu a2,(a1); \
|
|
ori a2,data; \
|
|
sw a0,BONITO_PCIMAP_CFG(bonito); \
|
|
lw zero,BONITO_PCIMAP_CFG(bonito); \
|
|
sb a2,(a1);
|
|
#define SUPERIO_WR(idx,data) \
|
|
li v0,BONITO_PCIIO_BASE_VA+0x3f0; \
|
|
or v1,zero,idx; \
|
|
sb v1,(v0); \
|
|
or v1,zero,data; \
|
|
sb v1,1(v0);
|
|
|
|
#define E2_EPP 2
|
|
#define E2_S1 (1<<2)
|
|
#define E2_S2 (1<<3)
|
|
#define E2_FLOPPY (1<<4)
|
|
|
|
LEAF(superio_init)
|
|
|
|
PCICONF_WRITEW(PCI_IDSEL_VIA686B,0,4,7);
|
|
/*positive decode*/
|
|
PCICONF_ORB(PCI_IDSEL_VIA686B,0,0x81,0x80);
|
|
PCICONF_WRITEB(PCI_IDSEL_VIA686B,0,0x83,0x80|0x1| 0x8);
|
|
PCICONF_WRITEB(PCI_IDSEL_VIA686B,0,0x85,3);
|
|
/* enable RTC/PS2/KBC */
|
|
PCICONF_WRITEB(PCI_IDSEL_VIA686B,0,0x5A,7);
|
|
|
|
SUPERIO_WR(0xe2,E2_S2|E2_S1|E2_EPP|E2_FLOPPY) /*enable serial and floppy */
|
|
SUPERIO_WR(0xe3,0x3f0>>2) /*floppy base address*/
|
|
SUPERIO_WR(0xe6,0x378>>2) /*parallel port*/
|
|
SUPERIO_WR(0xe7,0x3f8>>2) /*set serial port1 base addr 0x3f8*/
|
|
SUPERIO_WR(0xe8,0x2f8>>2) /*set serial port2 base addr 0x2f8*/
|
|
SUPERIO_WR(0xee,0xc0) /* both ports on high speed*/
|
|
|
|
PCICONF_WRITEB(PCI_IDSEL_VIA686B,0,0x85,1)
|
|
jr ra
|
|
nop
|
|
END(superio_init)
|
|
|
|
|
|
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