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280 lines
8.3 KiB
280 lines
8.3 KiB
#include "sb700.h"
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#include "rs780_cmn.h"
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extern struct southbridge_ati_sb700_config conf_info;
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#if 0
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static sata_drive_detect(int portnum, u32 iobar)
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{
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u8 byte, byte2;
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int i = 0;
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OUTB(0xA0 + 0x10 * (portnum % 2), iobar + 0x6);
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while (byte = INB(iobar + 0x6), byte2 = INB(iobar + 0x7),
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(byte != (0xA0 + 0x10 * (portnum % 2))) ||
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((byte2 & 0x88) != 0)) {
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printk_spew("0x6=%x, 0x7=%x\n", byte, byte2);
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if (byte != (0xA0 + 0x10 * (portnum % 2))) {
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/* This will happen at the first iteration of this loop
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* if the first SATA port is unpopulated and the
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* second SATA port is poulated.
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*/
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printk_debug("drive no longer selected after %d ms, "
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"retrying init\n", i * 10);
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return 1;
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} else
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printk_spew("drive detection not yet completed, "
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"waiting...\n");
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udelay(10000);
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i++;
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}
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printk_spew("drive detection done after %d ms\n", i * 10);
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return 0;
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}
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#endif
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static void sata_init(device_t dev)
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{
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u8 byte;
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u16 word;
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u32 dword;
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u32 sata_bar5;
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u32 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
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int i, j;
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u8 rev_id;
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struct southbridge_ati_sb700_config *conf = &conf_info;
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device_t sm_dev;
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/* SATA SMBus Disable */
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/* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */
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//sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
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sm_dev = _pci_make_tag(0, 0x14, 0);
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/* Disable SATA SMBUS */
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printk_info("Disable SATA SMBUS\n");
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byte = pci_read_config8(sm_dev, 0xad);
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byte |= (1 << 1);
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//pci_write_config8(sm_dev, 0xad, byte); //coreboot didn't do write action
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/* Enable SATA and power saving */
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printk_info("Enable SATA and power saving\n");
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byte = pci_read_config8(sm_dev, 0xad);
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byte |= (1 << 0);
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byte |= (1 << 5);
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pci_write_config8(sm_dev, 0xad, byte);
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/* Set the interrupt Mapping to INTG# */
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printk_info("Set the interrupt Mapping to INTG#\n");
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byte = pci_read_config8(sm_dev, 0xaf);
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byte = 0x6 << 2;
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pci_write_config8(sm_dev, 0xaf, byte);
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//add for sb700
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/* get rev_id */
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rev_id = pci_read_config8(sm_dev, 0x08) - 0x28;
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/* get base addresss */
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printk_info("get base address\n");
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sata_bar5 = (pci_read_config32(dev, 0x24) & ~0x3FF);
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sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7;
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sata_bar1 = pci_read_config16(dev, 0x14) & ~0x7;
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sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7;
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sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x7;
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sata_bar4 = pci_read_config16(dev, 0x20) & ~0x7;
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printk_spew("sata_bar0=%x\n", sata_bar0); /* 3030 */
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printk_spew("sata_bar1=%x\n", sata_bar1); /* 3070 */
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printk_spew("sata_bar2=%x\n", sata_bar2); /* 3040 */
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printk_spew("sata_bar3=%x\n", sata_bar3); /* 3080 */
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printk_spew("sata_bar4=%x\n", sata_bar4); /* 3000 */
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printk_spew("sata_bar5=%x\n", sata_bar5); /* e0309000 */
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#if 0 /* All SATA(six) interfaces work correctly in combined mode,
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* other didn't.
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*/
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//add for sb700
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/* disable combined mode to */
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printk_info("disable combined mode to\n");
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byte = pci_read_config8(sm_dev, 0xAD);
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byte &= ~(1 << 3);
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pci_write_config8(sm_dev, 0xAD, byte);
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#endif
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/* Program the 2C to 0x43801002 */
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printk_info("Program the 2C to 0x43801002\n");
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dword = 0x43801002;
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pci_write_config32(dev, 0x2c, dword);
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/* SERR-Enable */
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printk_info("serr-enable\n");
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word = pci_read_config16(dev, 0x04);
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word |= (1 << 8);
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pci_write_config16(dev, 0x04, word);
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/* Dynamic power saving */
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printk_info("Dynamic power saving\n");
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byte = pci_read_config8(dev, 0x40);
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byte |= (1 << 2);
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pci_write_config8(dev, 0x40, byte);
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/* Set SATA Operation Mode, Set to IDE mode */
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printk("Set SATA operation mode, set to IDE mode\n");
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byte = pci_read_config8(dev, 0x40);
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byte |= (1 << 0);
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byte |= (1 << 4);
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pci_write_config8(dev, 0x40, byte);
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dword = 0x01018f00; //bit[8]:1, Native PCI-mode, 0, Compability mode; bit[10]:1, Native PCI-mode, 0, Compability mode
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//dword = 0x01018a00;
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pci_write_config32(dev, 0x8, dword);
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byte = pci_read_config8(dev, 0x40);
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byte &= ~(1 << 0);
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pci_write_config8(dev, 0x40, byte);
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/* Enable the SATA watchdog counter */
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printk_info("Enable the SATA watchdog counter\n");
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byte = pci_read_config8(dev, 0x44);
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byte |= (1 << 0);
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pci_write_config8(dev, 0x44, byte);
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//add for sb700
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/* Set bit 29 and 24 for A12 */
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dword = pci_read_config32(dev, 0x40);
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if (rev_id < 0x14) /* before A12 */
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dword |= (1 << 29);
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else
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dword &= ~(1 << 29); /* A14 and above */
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pci_write_config32(dev, 0x40, dword);
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/* set bit 21 for A12 */
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dword = pci_read_config32(dev, 0x48);
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if (rev_id < 0x14) /* before A12 */
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dword |= 1 << 24 | 1 << 21;
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else {
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dword &= ~(1 << 24 | 1 << 21); /* A14 and above */
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dword &= ~0xFF80; /* 15:7 */
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dword |= 1 << 15 | 0x7F << 7;
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}
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pci_write_config32(dev, 0x48, dword);
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/* Program the watchdog counter to 0x10 */
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printk_info("Program the watchdog counter to 0x10\n");
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byte = 0x10;
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pci_write_config8(dev, 0x46, byte);
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/* RPR6.5 Program the PHY Global Control to 0x2C00 for A13 */
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printk_info("Program the PHY Global Control to 0x2C00 for A13\n");
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word = 0x2c00;
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pci_write_config16(dev, 0x86, word);
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/* RPR7.6.2 SATA GENI PHY ports setting */
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printk_info("sata geni phy ports setting\n");
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pci_write_config32(dev, 0x88, 0x01B48017);
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pci_write_config32(dev, 0x8c, 0x01B48016);
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pci_write_config32(dev, 0x90, 0x01B48016);
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pci_write_config32(dev, 0x94, 0x01B48016);
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pci_write_config32(dev, 0x98, 0x01B48016);
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pci_write_config32(dev, 0x9C, 0x01B48016);
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/* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */
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printk_info("sata gen II PHY port setting for port\n");
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pci_write_config16(dev, 0xA0, 0xA098);
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pci_write_config16(dev, 0xA2, 0xA098);
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pci_write_config16(dev, 0xA4, 0xA078);
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pci_write_config16(dev, 0xA6, 0xA078);
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pci_write_config16(dev, 0xA8, 0xA078);
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pci_write_config16(dev, 0xAA, 0xA078);
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/* Enable the I/O, MM, BusMaster access for SATA */
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printk_info("Enable the I/O, MM, BusMaster access for SATA\n");
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byte = pci_read_config8(dev, 0x4);
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byte |= 7 << 0;
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pci_write_config8(dev, 0x4, byte);
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/* RPR6.6 SATA drive detection. */
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/* Use BAR5+0x128,BAR0 for Primary Slave */
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/* Use BAR5+0x1A8,BAR0 for Primary Slave */
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/* Use BAR5+0x228,BAR2 for Secondary Master */
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/* Use BAR5+0x2A8,BAR2 for Secondary Slave */
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#ifdef EANBLE_SATA
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sata_bar5 = sata_bar5 | 0x80000000;
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sata_bar0 = sata_bar0 | 0xb8000000;
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sata_bar2 = sata_bar2 | 0xb8000000;
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for (i = 0; i < 4; i++) {
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byte = READB(sata_bar5 + 0x128 + 0x80 * i);
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printk_spew("SATA port %d status = %x\n", i, byte);
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byte &= 0xF;
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if( byte == 0x1 ) {
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/* If the drive status is 0x1 then we see it but we aren't talking to it. */
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/* Try to do something about it. */
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printk_spew("SATA device detected but not talking. Trying lower speed.\n");
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/* Read in Port-N Serial ATA Control Register */
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byte = READB(sata_bar5 + 0x12C + 0x80 * i);
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/* Set Reset Bit and 1.5g bit */
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byte |= 0x11;
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WRITEB(byte, (sata_bar5 + 0x12C + 0x80 * i));
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/* Wait 1ms */
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delay(1 * 1000);
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/* Clear Reset Bit */
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byte &= ~0x01;
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WRITEB(byte, (sata_bar5 + 0x12C + 0x80 * i));
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/* Wait 1ms */
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delay(1 * 1000);
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/* Reread status */
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byte = READB(sata_bar5 + 0x128 + 0x80 * i);
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printk_spew("SATA port %d status = %x\n", i, byte);
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byte &= 0xF;
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}
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if (byte == 0x3) {
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for (j = 0; j < 10; j++) {
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if (!sata_drive_detect(i, ((i / 2) == 0) ? sata_bar0 : sata_bar2))
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break;
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}
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printk_debug("%s %s device is %sready after %d tries\n",
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(i / 2) ? "Secondary" : "Primary",
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(i % 2 ) ? "Slave" : "Master",
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(j == 10) ? "not " : "",
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(j == 10) ? j : j + 1);
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} else {
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printk_debug("No %s %s SATA drive on Slot%d\n",
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(i / 2) ? "Secondary" : "Primary",
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(i % 2 ) ? "Slave" : "Master", i);
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}
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}
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#endif
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#if 0
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/* Below is CIM InitSataLateFar */
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/* Enable interrupts from the HBA */
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printk_info("Enable interrupts from the HBA\n");
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byte = READB(sata_bar5 + 0x4);
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byte |= 1 << 1;
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WRITEB(byte, (sata_bar5 + 0x4));
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/* Clear error status */
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printk_info("Clear error status\n");
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WRITEL(0xFFFFFFFF, (sata_bar5 + 0x130));
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WRITEL(0xFFFFFFFF, (sata_bar5 + 0x1b0));
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WRITEL(0xFFFFFFFF, (sata_bar5 + 0x230));
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WRITEL(0xFFFFFFFF, (sata_bar5 + 0x2b0));
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WRITEL(0xFFFFFFFF, (sata_bar5 + 0x330));
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WRITEL(0xFFFFFFFF, (sata_bar5 + 0x3b0));
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#endif
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/* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */
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/* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */
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/* word = 0x0000; */
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/* word = pm_ioread(0x28); */
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/* byte = pm_ioread(0x29); */
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/* word |= byte<<8; */
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/* printk_debug("AcpiGpe0Blk addr = %x\n", word); */
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/* writel(0x80000000 , word); */
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}
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