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103 lines
4.2 KiB
103 lines
4.2 KiB
Target Design Considerations
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Target Design Considerations
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Since the SerialICE Kernel requires minimal ROM and RAM, the main issue is how the
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SerialICE Controller will communicate with the Target.
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There are three basic choices:
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» An On-chip SerialICE Port
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» An On-board Commercial SIO
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» An Off-board Commercial SIO
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Whether the the SIO port is implemented onchip or offchip, it must be
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mapped into the target CPU's address space and connected to one of
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the processor's interrupt request inputs. The base address may be
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chosen to suit individual system requirements.
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If there are not enough unused interrupt request inputs to devote
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one solely to the SIO, it is possible to implement a software
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sharing scheme that would permit the application and the SerialICE Kernel
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to use the same interrupt request input.
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On-chip SerialICE Port
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The on-chip SerialICE Port offers the highest potential performance at the lowest
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cost of board real-estate. In most cases the small die area required will
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be insignificant. This is the preferred solution for new designs.
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The silicon area needed for such a simple function is very small (well
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below 1mm2), and, since the interface is serial, the pin count overhead
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is also very low.
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The reference onchip SIO design can support raw baud rates up to
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1.25Mbit/sec; allowing for communications overhead, the maximum data
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transfer rate during program downloads is around 50K Bytes/sec. This
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makes it possible to work with large download files.
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For such an onchip implementation, it will usually be most convenient
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to derive the clock rate for the SIO from the CPU clock, through a
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frequency divider. For systems in which the clock rate must be
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flexible, it may be supplied from an offchip source; however, this
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requires an additional package I/O pin.
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The fast serial connection between the SerialICE Manager and the debug
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target must provide good signal integrity. In general, long cable
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runs should be avoided, since transmission line effects may severely
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affect the operation of the link at high clock rates.
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Recommended Configuration
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» An 8-bit header within 2" of the SIO pins (pinout shown below). If
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this close proximity is not possible, then 47R series terminating resistors
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should be placed on all outputs from the target.
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This is important, since it affects the integrity of the high-speed
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signals running between the target system and the Pod. If the
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board traces running between the connector and the SIO device are too
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long, they will cause transmission-line effects which could make the
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interface's operation unreliable.
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The recommended connector presents 2 rows each of 4 pins, on the
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industry standard 2.5 mm (0.1") pitch IDC connector. These are listed
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below.
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Polarizing PinVCC
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GroundSerial Input (to target)
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GroundSerial Output (from target)
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GroundSerial Clock (to target)
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» A cable pod containing RS422 transceivers.
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Examples include the DS3695A devices offered
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by National Semiconductor Corp. These may be powered by the VCC feed from
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the 8-pin header. The pod should be connected to the target via
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8-way ribbon cable of no greater than 6" in length.
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» Good quality twisted pair data cable should be used for the
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connection between the pod and the SerialICE Controller.
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On-board Commercial SIO
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If it is not possible to integrate the SIO on-chip, a commercial SIO
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may be mounted on the Target. There is of course a penalty in board
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real-estate for this solution. But it may be used if board area is not
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critical.
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Off-board Commercial SIO
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In this solution a small daughter card containing a commercial SIO is
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connected to the Target via a small number of pins. This removes most
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of the board real-estate penalty, as it requires only the space needed
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for a small (approximately 25 pin) connector to connect an 8-bit
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peripheral to the CPU bus.
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In this way, standard production units carry only the minimal overhead
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of a small connector, yet can be used as development platforms at any
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time simply by plugging in the SIO card. In extremely cost sensitive
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applications, the debug connector position can simply be left open -
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reducing the overhead to a small amount of board area.
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