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417 lines
6.1 KiB
417 lines
6.1 KiB
#define i2cread newi2cread
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li msize,0
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PRINTSTR("DIMM read\r\n")
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/* only one memory slot, slave address is 1010000b */
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li sdCfg,0x04000000 /*bit 26突发式读写时的块内顺序*/
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li a1, 0x0
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li a0,0xa1
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bal i2cread
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nop
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beq v0,0xff,1f
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nop
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beq v0,0x80,1f
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nop
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move a0,v0
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bal hexserial
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nop
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PRINTSTR ("\r\nNo DIMM in slot 0 \r\n");
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b 2f
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nop
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1:
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or sdCfg, 0x1<<29
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nop
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li a0,0xa1
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bal ii2c_cfg
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nop
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2:
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li a1, 0x0
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li a0,0xa3
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bal i2cread
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nop
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li a1,0x0
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beq v0,0xff,1f
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nop
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beq v0,0x80,1f
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nop
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move a0,v0
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bal hexserial
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nop
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PRINTSTR ("\r\nNo DIMM in slot 1 \r\n");
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b 2f
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nop
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1:
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li a0,0xa3
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bal ii2c_cfg
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nop
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b 2f
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nop
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2:
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b 211f
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nop
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/*ic2 cfg
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* a0=0xa1 for slot 0,a0=0xa1 for slot 1
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* t5 used for save i2c addr a0,t6 save ra.
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*/
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LEAF(ii2c_cfg)
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move t6,ra
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move t5,a0
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#ifdef I2C_DEBUG
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li t1,0
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1:
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move a1,t1
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move a0,t5
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bal i2cread
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nop
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#print
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move a0, v0
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bal hexserial
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nop
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PRINTSTR("\r\n")
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addiu t1,t1,1
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li v0, 0x20
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bleu t1, v0, 1b
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nop
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#endif
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# set some parameters for DDR333
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# rank number and DDR type field will be filled later
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# to check: fix TCAS?
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PRINTSTR("read memory type\r\n")
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/* read DIMM number of rows */
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move a0,t5 /* #zgj-11-17 */
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li a1,3
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bal i2cread
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nop
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move a0, v0
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subu v0, 12
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bgtu v0, 2,.nodimm1
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nop
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move t1, v0
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PRINTSTR("read number of rows\r\n")
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2: /* read DIMM number of cols */
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move a0,t5 /* #zgj-11-17 */
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li a1,4
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bal i2cread
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nop
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subu v0, 8
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bgtu v0, 4,.nodimm1
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nop
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bne t1, 0, 10f
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nop
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bne v0, 2, 20f
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nop
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li v0, 0
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b .ddrtype1
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nop
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20: bne v0, 1, 21f
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nop
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li v0, 1
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b .ddrtype1
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nop
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21: bne v0, 0, 22f
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nop
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li v0, 2
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b .ddrtype1
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nop
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22: bne v0, 3, 33f
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nop
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li v0, 3
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b .ddrtype1
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nop
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10: bne t1, 1, 11f
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nop
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bne v0, 3, 20f
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nop
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li v0, 4
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b .ddrtype1
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nop
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20: bne v0, 2, 21f
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nop
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li v0, 5
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b .ddrtype1
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nop
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21: bne v0, 1, 22f
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nop
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li v0, 6
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b .ddrtype1
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nop
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22: bne v0, 4, 33f
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nop
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li v0, 7
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b .ddrtype1
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nop
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11: bne t1, 2, 33f
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nop
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bne v0, 4, 20f
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nop
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li v0, 8
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b .ddrtype1
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nop
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20: bne v0, 3, 21f
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nop
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li v0, 9
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b .ddrtype1
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nop
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21: bne v0, 2, 33f
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nop
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li v0, 10
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b .ddrtype1
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nop
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33: PRINTSTR("DDR type not supported!\r\n");
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34: b 34b
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nop
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.ddrtype1:
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#bit 25:22 is DDR type field
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sll v0, 22
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and v0,0x03c00000
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or sdCfg,v0
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/* read DDR RATE*/
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move a0,t5
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li a1,23
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bal i2cread
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nop
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beq v0,0xa0,40f
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nop
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beq v0,0x75,41f
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nop
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beq v0,0x60,42f
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nop
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b 42f
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nop
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/* config sdCfg bits [ 9:0 ] */
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40: /* ddr200 */
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or sdCfg,0x0b1
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b 47f
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nop
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41: /* ddr266 */
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or sdCfg,0x3ae
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b 47f
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nop
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42: /* ddr333 */
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or sdCfg,0x3df
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b 47f
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nop
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#####################################################
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/* read DDR SDRAM Minimum Clock Cycle when CL is Derated by One Clock,config sdCfg [ 21:10 ]*/
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47:
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move a0,t5
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li a1,25
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bal i2cread
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nop
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beq v0,0xa0,40f
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nop
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beq v0,0x75,41f
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nop
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beq v0,0x60,42f
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nop
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b 41f
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nop
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40: /* ddr200 */
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move a0,t5
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li a1,12
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bal i2cread
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nop
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bne v0,0x82,10f
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nop
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or sdCfg,780<<10
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b 45f
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nop
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10:
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bne v0,0x80,.nodimm1
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nop
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or sdCfg,1560<<10
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b 45f
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nop
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41: /* ddr266 */
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move a0,t5
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li a1,12
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bal i2cread
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nop
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bne v0,0x82,11f
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nop
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or sdCfg,1040<<10
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b 45f
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nop
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11:
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bne v0,0x80,.nodimm1
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nop
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or sdCfg,2080<<10
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b 45f
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nop
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42: /* ddr333 */
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move a0,t5
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li a1,12
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bal i2cread
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nop
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bne v0,0x82,12f
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nop
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or sdCfg,1300<<10
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b 45f
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nop
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12:
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bne v0,0x80,.nodimm1
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nop
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or sdCfg,2600<<10
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b 45f
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nop
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#####################################################
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/* Minimum Ras to Cas Delay (tRCD)
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move a0,t5
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bal i2cread
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li a1,29
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or */
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45:
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2: /* read DIMM number of blocks-per-ddrram */
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move a0,t5 /* #zgj-11-17 */
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li a1,17
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bal i2cread
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nop
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beq v0,2,2f
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nop
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bne v0,4,.nodimm1
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nop
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PRINTSTR("read blocks per ddrram\r\n");
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2: /* read DIMM number of sides (banks) */
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move a0,t5 /* #zgj-11-17 */
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li a1,5
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bal i2cread
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nop
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beq v0,1,2f
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nop
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bne v0,2,.nodimm1
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nop
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or sdCfg, 0x1<<27
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PRINTSTR("read number of sides\r\n") ;
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2: /* read DIMM width */
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move a0,t5 /* #zgj-11-17 */
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li a1,6
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bal i2cread
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nop
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bleu v0,36,2f
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nop
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bgtu v0,72,.nodimm1
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nop
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PRINTSTR("read width\r\n") ;
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2:
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move a0,t5
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li a1,31
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bal i2cread
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nop
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beqz v0,.nodimm1
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nop
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sll tmpsize,v0,22 # multiply by 4M
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addu msize,tmpsize
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move a0,t5
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li a1,5
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bal i2cread
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nop
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beq v0,1,1f
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nop
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addu msize,tmpsize
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b 1f
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nop
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.nodimm1:
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PRINTSTR ("\r\nNo DIMM in this slot ");
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1:
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jr t6
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nop
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END(ii2c_cfg)
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LEAF(i2cread)
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/* set device address */
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li v0, 0xbfd00000 + SMBUS_HOST_ADDRESS
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sb a0, 0(v0);
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/* store register offset */
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li v0, 0xbfd00000 + SMBUS_HOST_COMMAND
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sb a1, 0(v0);
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/* read byte data protocol */
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li v0, 0x08
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li v1, 0xbfd00000 + SMBUS_HOST_CONTROL
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sb v0, 0(v1);
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/* make sure SMB host ready to start, important!--zfx */
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li v1, 0xbfd00000 + SMBUS_HOST_STATUS
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lbu v0, 0(v1)
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andi v0,v0, 0x1f
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beqz v0,1f
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nop
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sb v0, 0(v1)
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lbu v0, 0(v1) #flush the write
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1:
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/* start */
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li v1, 0xbfd00000 + SMBUS_HOST_CONTROL
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lbu v0, 0(v1)
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ori v0, v0, 0x40
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sb v0, 0(v1);
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/* wait */
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li v1, 0xbfd00000 + SMBUS_HOST_STATUS
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1:
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#if 0
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/* delay */
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li a0, 0x1000
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2:
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bnez a0,2b
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addiu a0, -1
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#endif
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lbu v0, 0(v1)
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andi v0, SMBUS_HOST_STATUS_BUSY
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bnez v0, 1b #IDEL ?
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nop
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li v1, 0xbfd00000 + SMBUS_HOST_STATUS
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lbu v0, 0(v1)
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andi v0,v0, 0x1f
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beqz v0,1f
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nop
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sb v0, 0(v1) #reset
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lbu v0, 0(v1) #flush the write
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1:
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li v1, 0xbfd00000 + SMBUS_HOST_DATA0
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lbu v0, 0(v1)
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jr ra
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nop
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END(i2cread)
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211:
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#undef i2cread
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######################################################################################################
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