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468 lines
12 KiB
468 lines
12 KiB
/* $Id: pci_machdep.c,v 1.1.1.1 2006/09/14 01:59:09 root Exp $ */
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/*
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* Copyright (c) 2001 Opsycon AB (www.opsycon.se)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Opsycon AB, Sweden.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/param.h>
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#include <sys/device.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/nppbreg.h>
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#include <machine/bus.h>
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#include "include/bonito.h"
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#include <pmon.h>
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extern void *pmalloc __P((size_t ));
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#if (PCI_IDSEL_CS5536 != 0)
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#include <include/cs5536_pci.h>
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extern pcireg_t cs5536_pci_conf_readn(int function, int reg, int width);
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extern int cs5536_pci_conf_writen(int function, int reg, int width, pcireg_t value);
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#endif
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extern void *pmalloc __P((size_t ));
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extern int _pciverbose;
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extern char hwethadr[6];
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struct pci_device *_pci_bus[16];
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int _max_pci_bus = 0;
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/* PCI mem regions in PCI space */
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/* soft versions of above */
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static pcireg_t pci_local_mem_pci_base;
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/****************************/
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/*initial PCI */
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/****************************/
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int
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_pci_hwinit(initialise, iot, memt)
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int initialise;
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bus_space_tag_t iot;
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bus_space_tag_t memt;
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{
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/*pcireg_t stat;*/
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struct pci_device *pd;
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struct pci_bus *pb;
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int newcfg=0;
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SBD_DISPLAY ("HW-0", 0);
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if(getenv("newcfg"))newcfg=1;
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if (!initialise) {
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return(0);
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}
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SBD_DISPLAY ("HW-1", 0);
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/*
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* Allocate and initialize PCI bus heads.
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*/
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/*
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* PCI Bus 0
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*/
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pd = pmalloc(sizeof(struct pci_device));
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pb = pmalloc(sizeof(struct pci_bus));
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if(pd == NULL || pb == NULL) {
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printf("pci: can't alloc memory. pci not initialized\n");
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return(-1);
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}
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SBD_DISPLAY ("HW-2", 0);
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pd->pa.pa_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
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pd->pa.pa_iot = pmalloc(sizeof(bus_space_tag_t));
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pd->pa.pa_iot->bus_reverse = 1;
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pd->pa.pa_iot->bus_base = BONITO_PCIIO_BASE_VA;
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//printf("pd->pa.pa_iot=%p,bus_base=0x%x\n",pd->pa.pa_iot,pd->pa.pa_iot->bus_base);
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pd->pa.pa_memt = pmalloc(sizeof(bus_space_tag_t));
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pd->pa.pa_memt->bus_reverse = 1;
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pd->pa.pa_dmat = &bus_dmamap_tag;
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pd->bridge.secbus = pb;
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_pci_head = pd;
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SBD_DISPLAY ("HW-3", 0);
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if(newcfg)
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{
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pb->minpcimemaddr = 0x14000000;//������,���ܺ�linux������ʼ��ַһ��,����xwindow����ʾ������
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pb->nextpcimemaddr = 0x1c000000;
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pd->pa.pa_memt->bus_base = 0xa0000000;
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BONITO_PCIMAP =
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BONITO_PCIMAP_WIN(0, PCI_MEM_SPACE_PCI_BASE+0x00000000) |
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BONITO_PCIMAP_WIN(1, PCI_MEM_SPACE_PCI_BASE+0x14000000) |
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BONITO_PCIMAP_WIN(2, PCI_MEM_SPACE_PCI_BASE+0x18000000) |
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BONITO_PCIMAP_PCIMAP_2;
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}
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else
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{
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/*pci��ַ��cpu��ַ����,����pci memʱҪioreamapת��,ֱ��or 0xb0000000*/
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pb->minpcimemaddr = 0x04000000;
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pb->nextpcimemaddr = 0x0c000000;
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pd->pa.pa_memt->bus_base = 0xb0000000;
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BONITO_PCIMAP =
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BONITO_PCIMAP_WIN(0, PCI_MEM_SPACE_PCI_BASE+0x10000000) |
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BONITO_PCIMAP_WIN(1, PCI_MEM_SPACE_PCI_BASE+0x40000000) |
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BONITO_PCIMAP_WIN(2, PCI_MEM_SPACE_PCI_BASE+0x44000000) |
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BONITO_PCIMAP_PCIMAP_2;
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}
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SBD_DISPLAY ("HW-4", 0);
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pb->minpciioaddr = 0x0004000;
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pb->nextpciioaddr = BONITO_PCIIO_SIZE;
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pb->pci_mem_base = 0xb0000000;
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pb->pci_io_base = 0xbfd00000;
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pb->max_lat = 255;
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pb->fast_b2b = 1;
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pb->prefetch = 1;
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pb->bandwidth = 4000000;
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pb->ndev = 1;
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_pci_bushead = pb;
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_pci_bus[_max_pci_bus++] = pd;
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SBD_DISPLAY ("HW-5", 0);
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bus_dmamap_tag._dmamap_offs = 0;
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/*set pci base0 address and window size*/
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pci_local_mem_pci_base = 0x80000000;
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BONITO_PCIBASE0 = 0x80000000;
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BONITO_PCIBASE1 = 0;
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BONITO(BONITO_REGBASE + 0x50) = 0x8000000c;
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BONITO(BONITO_REGBASE + 0x54) = 0xffffffff;
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SBD_DISPLAY ("HW-6", 0);
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/*set master1's window0 to map pci 2G->DDR 0 */
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asm(".set mips3;dli $2,0x900000003ff00100;dli $3,0x80000000;sd $3,0x0($2);dli $3,0xffffffff80000000;sd $3,0x40($2);li $3,0xf0;sd $3,0x80($2);.set mips0" :::"$2","$3");
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SBD_DISPLAY ("HW-7", 0);
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#if 1
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/*
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* PCI to local mapping: [8M,16M] -> [8M,16M]
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*/
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BONITO_PCI_REG(0x18) = 0x00800000;
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SBD_DISPLAY ("H1-7", 0);
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BONITO_PCI_REG(0x1c) = 0x0;
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SBD_DISPLAY ("H2-7", 0);
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BONITO(BONITO_REGBASE + 0x58) = 0xff80000c;
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SBD_DISPLAY ("H3-7", 0);
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BONITO(BONITO_REGBASE + 0x5c) = 0xffffffff;
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SBD_DISPLAY ("H4-7", 0);
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/*set pci 8-16M -> DDR 8-16M ,window size 8M,can not map 0-8M to pci,because ddr pci address will cover vga mem.*/
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asm(".set mips3;dli $2,0x900000003ff00100;li $3,0x800000;sd $3,0x08($2);dli $3,0xffffffffff800000;sd $3,0x48($2);li $3,0x8000f0;sd $3,0x88($2);.set mips0" :::"$2","$3");
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SBD_DISPLAY ("HW-8", 0);
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#endif
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SBD_DISPLAY ("HW-9", 0);
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{
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/* can not change gnt to break pci transfer when device's gnt not deassert for some sb like 82371,via686b. */
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#ifdef CONFIG_SLOW_PCI_FOR_BROKENDEV
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/*
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also make default pci device not cpu itselt,this will make two cpu accesses to pci has about 5 pci clocks inteval for broken device like sundance net adaptor,
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otherwise maybe only one pci clock inteval.
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*/
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*(volatile int *)0xbfe00168=0x00fe0115;
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#else
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*(volatile int *)0xbfe00168=0x00fe0105;
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#endif
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/* make pci retry max 32. */
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// *(volatile int *)0xbfe00058 |= 0x2000;
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}
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return(1);
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}
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/*
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* Called to reinitialise the bridge after we've scanned each PCI device
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* and know what is possible. We also set up the interrupt controller
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* routing and level control registers.
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*/
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void
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_pci_hwreinit (void)
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{
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}
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void
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_pci_flush (void)
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{
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}
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/*
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* Map the CPU virtual address of an area of local memory to a PCI
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* address that can be used by a PCI bus master to access it.
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*/
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vm_offset_t
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_pci_dmamap(va, len)
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vm_offset_t va;
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unsigned int len;
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{
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#if 0
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return(VA_TO_PA(va) + bus_dmamap_tag._dmamap_offs);
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#endif
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return(pci_local_mem_pci_base + VA_TO_PA (va));
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}
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#if 1
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/*
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* Map the PCI address of an area of local memory to a CPU physical
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* address.
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*/
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vm_offset_t
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_pci_cpumap(pcia, len)
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vm_offset_t pcia;
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unsigned int len;
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{
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return PA_TO_VA(pcia - pci_local_mem_pci_base);
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}
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#endif
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/*
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* Make pci tag from bus, device and function data.
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*/
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pcitag_t
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_pci_make_tag(bus, device, function)
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int bus;
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int device;
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int function;
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{
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pcitag_t tag;
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tag = (bus << 16) | (device << 11) | (function << 8);
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return(tag);
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}
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/*
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* Break up a pci tag to bus, device function components.
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*/
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void
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_pci_break_tag(tag, busp, devicep, functionp)
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pcitag_t tag;
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int *busp;
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int *devicep;
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int *functionp;
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{
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if (busp) {
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*busp = (tag >> 16) & 255;
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}
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if (devicep) {
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*devicep = (tag >> 11) & 31;
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}
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if (functionp) {
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*functionp = (tag >> 8) & 7;
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}
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}
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int
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_pci_canscan (pcitag_t tag)
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{
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int bus, device, function;
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_pci_break_tag (tag, &bus, &device, &function);
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if((bus == 0 ) && device == 0) {
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return(0); /* Ignore the Discovery itself */
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}
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return (1);
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}
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pcireg_t
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_pci_conf_read(pcitag_t tag,int reg)
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{
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return _pci_conf_readn(tag,reg,4);
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}
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pcireg_t
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_pci_conf_readn(pcitag_t tag, int reg, int width)
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{
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u_int32_t addr, type;
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pcireg_t data;
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int bus, device, function;
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if ((reg & (width-1)) || reg < 0 || reg >= 0x100) {
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if (_pciverbose >= 1)
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_pci_tagprintf (tag, "_pci_conf_read: bad reg 0x%x\n", reg);
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return ~0;
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}
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_pci_break_tag (tag, &bus, &device, &function);
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if (bus == 0) {
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/* Type 0 configuration on onboard PCI bus */
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if (device > 20 || function > 7)
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return ~0; /* device out of range */
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addr = (1 << (device+11)) | (function << 8) | reg;
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type = 0x00000;
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}
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else {
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/* Type 1 configuration on offboard PCI bus */
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if (bus > 255 || device > 31 || function > 7)
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return ~0; /* device out of range */
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addr = (bus << 16) | (device << 11) | (function << 8) | reg;
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type = 0x10000;
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}
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#if (PCI_IDSEL_CS5536 != 0)
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if( (bus == 0) && (device == PCI_IDSEL_CS5536) && (reg < 0xf0) ){
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return cs5536_pci_conf_readn(function, reg, width);
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}
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#endif
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/* clear aborts */
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BONITO_PCICMD |= PCI_STATUS_MASTER_ABORT | PCI_STATUS_MASTER_TARGET_ABORT;
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BONITO_PCIMAP_CFG = (addr >> 16) | type;
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data = *(volatile pcireg_t *)PHYS_TO_UNCACHED(BONITO_PCICFG_BASE | (addr & 0xfffc));
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/* move data to correct position */
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data = data >> ((addr & 3) << 3);
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if (BONITO_PCICMD & PCI_STATUS_MASTER_ABORT) {
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BONITO_PCICMD |= PCI_STATUS_MASTER_ABORT;
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#if 0
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if (_pciverbose >= 1)
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_pci_tagprintf (tag, "_pci_conf_read: reg=%x master abort\n", reg);
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#endif
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return ~0;
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}
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if (BONITO_PCICMD & PCI_STATUS_MASTER_TARGET_ABORT) {
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BONITO_PCICMD |= PCI_STATUS_MASTER_TARGET_ABORT;
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if (_pciverbose >= 1)
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_pci_tagprintf (tag, "_pci_conf_read: target abort\n");
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return ~0;
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}
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return data;
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}
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void
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_pci_conf_write(pcitag_t tag, int reg, pcireg_t data)
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{
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return _pci_conf_writen(tag,reg,data,4);
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}
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void
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_pci_conf_writen(pcitag_t tag, int reg, pcireg_t data,int width)
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{
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u_int32_t addr, type;
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int bus, device, function;
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if ((reg &(width-1)) || reg < 0 || reg >= 0x100) {
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if (_pciverbose >= 1)
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_pci_tagprintf (tag, "_pci_conf_write: bad reg %x\n", reg);
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return;
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}
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_pci_break_tag (tag, &bus, &device, &function);
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if (bus == 0) {
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/* Type 0 configuration on onboard PCI bus */
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if (device > 20 || function > 7)
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return; /* device out of range */
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addr = (1 << (device+11)) | (function << 8) | reg;
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type = 0x00000;
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}
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else {
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/* Type 1 configuration on offboard PCI bus */
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if (bus > 255 || device > 31 || function > 7)
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return; /* device out of range */
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addr = (bus << 16) | (device << 11) | (function << 8) | reg;
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type = 0x10000;
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}
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#if (PCI_IDSEL_CS5536 != 0)
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if( (bus == 0) && (device == PCI_IDSEL_CS5536) & (reg < 0xf0)){
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if(cs5536_pci_conf_writen(function, reg, width, data)){
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printf("cs5536 write error.\n");
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}
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return;
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}
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#endif
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/* clear aborts */
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BONITO_PCICMD |= PCI_STATUS_MASTER_ABORT | PCI_STATUS_MASTER_TARGET_ABORT;
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BONITO_PCIMAP_CFG = (addr >> 16)|type;
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#if 0
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*(volatile pcireg_t *)PHYS_TO_UNCACHED(BONITO_PCICFG_BASE | (addr & 0xfffc)) = data;
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#else
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{
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pcireg_t ori = *(volatile pcireg_t *)PHYS_TO_UNCACHED(BONITO_PCICFG_BASE | (addr & 0xfffc));
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pcireg_t mask = 0x0;
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if (width == 2) {
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if (addr & 3) mask = 0xffff;
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else mask = 0xffff0000;
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}else if (width == 1) {
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if ((addr & 3) == 1) {
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mask = 0xffff00ff;
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}else if ((addr & 3) == 2) {
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mask = 0xff00ffff;
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}else if ((addr & 3) == 3) {
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mask = 0x00ffffff;
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}else{
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mask = 0xffffff00;
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}
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}
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data = data << ((addr & 3) << 3);
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data = (ori & mask) | data;
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*(volatile pcireg_t *)PHYS_TO_UNCACHED(BONITO_PCICFG_BASE | (addr & 0xfffc)) = data;
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}
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#endif
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if (BONITO_PCICMD & PCI_STATUS_MASTER_ABORT) {
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BONITO_PCICMD |= PCI_STATUS_MASTER_ABORT;
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if (_pciverbose >= 1)
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_pci_tagprintf (tag, "_pci_conf_write: master abort\n");
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}
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if (BONITO_PCICMD & PCI_STATUS_MASTER_TARGET_ABORT) {
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BONITO_PCICMD |= PCI_STATUS_MASTER_TARGET_ABORT;
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if (_pciverbose >= 1)
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_pci_tagprintf (tag, "_pci_conf_write: target abort\n");
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}
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}
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void
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pci_sync_cache(p, adr, size, rw)
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void *p;
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vm_offset_t adr;
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size_t size;
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int rw;
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{
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CPU_IOFlushDCache(adr, size, rw);
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}
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