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71 lines
2.0 KiB
71 lines
2.0 KiB
<title>PMON Limitations</title>
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<h1 align="center">PMON Limitations</h1>
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<!--INDEX "PMON limitations" -->
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<!--INDEX "k0 register" "k1 register" "Breakpoints in exception handlers" -->
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When the target system is halted at a breakpoint, it's possible to save
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the contents of most general purpose registers. However, in this scheme,
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the contents of two general purpose registers must be
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sacrificed; two registers are required for use by the PMON code
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that extracts the contents of the other general purpose registers. The
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registers chosen are k0 and k1 because those are the only two registers
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that are guaranteed (by convention) to not contain useful values when
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interrupts are enabled. Users should
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keep in mind that the contents of these registers at the time of a
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breakpoint are therefore not available. <p>
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It should also be noted that PMON makes use of the CPU's
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exception handling mechanism whenever a breakpoint occurs. Therefore,
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care must be taken in debugging exception handlers, to ensure that any
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necessary machine state is saved before a debug exception may occur. In
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particular, the EPC (Exception Program Counter), and SR (Status
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Register) must be saved, along with any other registers which may be
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used by the handler.<p>
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In practice, this means that breakpoints or single-stepping may safely
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be used within the body of an exception handler, provided it is written
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in such a way that all necessary state is saved as its initial action
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on entry. However neither of these features may be used during the
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first few instructions of the handler; these must be allowed to
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complete the task of saving essential machine state to the stack. <p>
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<p><hr>
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<p><b>Navigation:</b> <a href="pmon.htm">Document Home</a> | <a href="doctoc.htm">Document
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Contents</a> | <a href="docindex.htm">Document Index</a></p>
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<p><!--$Id: pmonlim.htm,v 1.1.1.1 2006/09/14 01:59:06 root Exp $ --> </p>
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<p>
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