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253 lines
11 KiB
253 lines
11 KiB
#ifndef _LS2H_H
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#define _LS2H_H
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#define LS2H_IO_REG_BASE 0xbb000000
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/* CHIP CONFIG regs */
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#define LS2H_CHIP_CFG_REG_BASE (LS2H_IO_REG_BASE + 0x00d00000)
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#define LS2H_MSI_PORT_REG (LS2H_CHIP_CFG_REG_BASE + 0x0)
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#define LS2H_INT_REG_BASE (LS2H_CHIP_CFG_REG_BASE + 0x0040)
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#define LS2H_INT_ISR0_REG (LS2H_CHIP_CFG_REG_BASE + 0x0040)
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#define LS2H_INT_IEN0_REG (LS2H_CHIP_CFG_REG_BASE + 0x0044)
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#define LS2H_INT_SET0_REG (LS2H_CHIP_CFG_REG_BASE + 0x0048)
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#define LS2H_INT_CLR0_REG (LS2H_CHIP_CFG_REG_BASE + 0x004c)
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#define LS2H_INT_POL0_REG (LS2H_CHIP_CFG_REG_BASE + 0x0050)
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#define LS2H_INT_EDGE0_REG (LS2H_CHIP_CFG_REG_BASE + 0x0054)
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#define LS2H_GPIO_CFG_REG (LS2H_CHIP_CFG_REG_BASE + 0x00c0)
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#define LS2H_GPIO_OUT_EN_REG (LS2H_CHIP_CFG_REG_BASE + 0x00c4)
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#define LS2H_GPIO_IN_REG (LS2H_CHIP_CFG_REG_BASE + 0x00c8)
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#define LS2H_GPIO_OUT_REG (LS2H_CHIP_CFG_REG_BASE + 0x00cc)
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#define LS2H_DMA_ORDER_REG (LS2H_CHIP_CFG_REG_BASE + 0x0100)
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#define LS2H_CHIP_CFG0_REG (LS2H_CHIP_CFG_REG_BASE + 0x0200)
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#define LS2H_CHIP_CFG1_REG (LS2H_CHIP_CFG_REG_BASE + 0x0204)
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#define LS2H_CHIP_CFG2_REG (LS2H_CHIP_CFG_REG_BASE + 0x0208)
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#define LS2H_CHIP_CFG3_REG (LS2H_CHIP_CFG_REG_BASE + 0x020c)
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#define LS2H_CHIP_SAMP0_REG (LS2H_CHIP_CFG_REG_BASE + 0x0210)
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#define LS2H_CHIP_SAMP1_REG (LS2H_CHIP_CFG_REG_BASE + 0x0214)
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#define LS2H_CHIP_SAMP2_REG (LS2H_CHIP_CFG_REG_BASE + 0x0218)
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#define LS2H_CHIP_SAMP3_REG (LS2H_CHIP_CFG_REG_BASE + 0x021c)
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#define LS2H_CHIP_SAMP4_REG (LS2H_CHIP_CFG_REG_BASE + 0x00d8)
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#define LS2H_CHIP_SAMP5_REG (LS2H_CHIP_CFG_REG_BASE + 0x00e8)
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#define LS2H_CLK_CTRL0_REG (LS2H_CHIP_CFG_REG_BASE + 0x0220)
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#define LS2H_CLK_CTRL1_REG (LS2H_CHIP_CFG_REG_BASE + 0x0224)
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#define LS2H_CLK_CTRL2_REG (LS2H_CHIP_CFG_REG_BASE + 0x0228)
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#define LS2H_CLK_CTRL3_REG (LS2H_CHIP_CFG_REG_BASE + 0x022c)
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#define LS2H_PIXCLK0_CTRL0_REG (LS2H_CHIP_CFG_REG_BASE + 0x0230)
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#define LS2H_PIXCLK0_CTRL1_REG (LS2H_CHIP_CFG_REG_BASE + 0x0234)
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#define LS2H_PIXCLK1_CTRL0_REG (LS2H_CHIP_CFG_REG_BASE + 0x0238)
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#define LS2H_PIXCLK1_CTRL1_REG (LS2H_CHIP_CFG_REG_BASE + 0x023c)
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#define LS2H_CLOCK_CTRL0_REG (LS2H_CHIP_CFG_REG_BASE + 0x0220)
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#define LS2H_CLOCK_CTRL1_REG (LS2H_CHIP_CFG_REG_BASE + 0x0224)
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#define LS2H_CLOCK_CTRL2_REG (LS2H_CHIP_CFG_REG_BASE + 0x0228)
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#define LS2H_CLOCK_CTRL3_REG (LS2H_CHIP_CFG_REG_BASE + 0x022c)
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#define LS2H_WIN_CFG_BASE (LS2H_CHIP_CFG_REG_BASE + 0x80000)
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#define LS2H_M4_WIN0_BASE_REG (LS2H_WIN_CFG_BASE + 0x0400)
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#define LS2H_M4_WIN0_MASK_REG (LS2H_WIN_CFG_BASE + 0x0440)
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#define LS2H_M4_WIN0_MMAP_REG (LS2H_WIN_CFG_BASE + 0x0480)
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#define LS2H_QOS_CFG6_REG (LS2H_WIN_CFG_BASE + 0x0630)
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/* USB regs */
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#define LS2H_EHCI_REG_BASE (LS2H_IO_REG_BASE + 0x00e00000)
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#define LS2H_OHCI_REG_BASE (LS2H_IO_REG_BASE + 0x00e08000)
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/* GMAC regs */
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#define LS2H_GMAC0_REG_BASE (LS2H_IO_REG_BASE + 0x00e10000)
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#define LS2H_GMAC1_REG_BASE (LS2H_IO_REG_BASE + 0x00e18000)
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/* HDA regs */
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#define LS2H_HDA_REG_BASE (LS2H_IO_REG_BASE + 0x00e20000)
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/* SATAregs */
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#define LS2H_SATA_REG_BASE (LS2H_IO_REG_BASE + 0x00e30000)
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/* GPU regs */
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#define LS2H_GPU_REG_BASE (LS2H_IO_REG_BASE + 0x00e40000)
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/* DC regs */
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#define LS2H_DC_REG_BASE (LS2H_IO_REG_BASE + 0x00e50000)
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#define LS2H_FB_CFG_DVO_REG (LS2H_DC_REG_BASE + 0x1240)
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#define LS2H_FB_CFG_VGA_REG (LS2H_DC_REG_BASE + 0x1250)
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#define LS2H_FB_ADDR0_DVO_REG (LS2H_DC_REG_BASE + 0x1260)
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#define LS2H_FB_ADDR0_VGA_REG (LS2H_DC_REG_BASE + 0x1270)
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#define LS2H_FB_ADDR1_DVO_REG (LS2H_DC_REG_BASE + 0x1580)
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#define LS2H_FB_ADDR1_VGA_REG (LS2H_DC_REG_BASE + 0x1590)
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#define LS2H_FB_STRI_DVO_REG (LS2H_DC_REG_BASE + 0x1280)
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#define LS2H_FB_STRI_VGA_REG (LS2H_DC_REG_BASE + 0x1290)
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#define LS2H_FB_CUR_CFG_REG (LS2H_DC_REG_BASE + 0x1520)
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#define LS2H_FB_CUR_ADDR_REG (LS2H_DC_REG_BASE + 0x1530)
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#define LS2H_FB_CUR_LOC_ADDR_REG (LS2H_DC_REG_BASE + 0x1540)
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#define LS2H_FB_CUR_BACK_REG (LS2H_DC_REG_BASE + 0x1550)
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#define LS2H_FB_CUR_FORE_REG (LS2H_DC_REG_BASE + 0x1560)
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#define LS2H_FB_DAC_CTRL_REG (LS2H_DC_REG_BASE + 0x1600)
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/* OTG regs */
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#define LS2H_OTG_REG_BASE (LS2H_IO_REG_BASE + 0x00e60000)
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/* SPI regs */
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#define LS2H_SPI_REG_BASE (LS2H_IO_REG_BASE + 0x00e70000)
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/* UART regs */
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#define LS2H_UART0_REG_BASE (LS2H_IO_REG_BASE + 0x00e80000)
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#define LS2H_UART1_REG_BASE (LS2H_IO_REG_BASE + 0x00e81000)
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#define LS2H_UART2_REG_BASE (LS2H_IO_REG_BASE + 0x00e82000)
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#define LS2H_UART3_REG_BASE (LS2H_IO_REG_BASE + 0x00e83000)
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/* I2C regs */
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#define LS2H_I2C0_REG_BASE (LS2H_IO_REG_BASE + 0x00e90000)
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#define LS2H_I2C0_PRER_LO_REG (LS2H_I2C0_REG_BASE + 0x0)
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#define LS2H_I2C0_PRER_HI_REG (LS2H_I2C0_REG_BASE + 0x1)
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#define LS2H_I2C0_CTR_REG (LS2H_I2C0_REG_BASE + 0x2)
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#define LS2H_I2C0_TXR_REG (LS2H_I2C0_REG_BASE + 0x3)
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#define LS2H_I2C0_RXR_REG (LS2H_I2C0_REG_BASE + 0x3)
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#define LS2H_I2C0_CR_REG (LS2H_I2C0_REG_BASE + 0x4)
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#define LS2H_I2C0_SR_REG (LS2H_I2C0_REG_BASE + 0x4)
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#define LS2H_I2C1_REG_BASE (LS2H_IO_REG_BASE + 0x00e91000)
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#define LS2H_I2C1_PRER_LO_REG (LS2H_I2C1_REG_BASE + 0x0)
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#define LS2H_I2C1_PRER_HI_REG (LS2H_I2C1_REG_BASE + 0x1)
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#define LS2H_I2C1_CTR_REG (LS2H_I2C1_REG_BASE + 0x2)
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#define LS2H_I2C1_TXR_REG (LS2H_I2C1_REG_BASE + 0x3)
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#define LS2H_I2C1_RXR_REG (LS2H_I2C1_REG_BASE + 0x3)
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#define LS2H_I2C1_CR_REG (LS2H_I2C1_REG_BASE + 0x4)
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#define LS2H_I2C1_SR_REG (LS2H_I2C1_REG_BASE + 0x4)
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#define CR_START 0x80
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#define CR_STOP 0x40
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#define CR_READ 0x20
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#define CR_WRITE 0x10
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#define CR_ACK 0x8
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#define CR_IACK 0x1
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#define SR_NOACK 0x80
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#define SR_BUSY 0x40
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#define SR_AL 0x20
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#define SR_TIP 0x2
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#define SR_IF 0x1
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/* PWM regs */
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#define LS2H_PWM_REG_BASE (LS2H_IO_REG_BASE + 0x00ea0000)
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/* HPET regs */
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#define LS2H_HPET_REG_BASE (LS2H_IO_REG_BASE + 0x00ec0000)
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/* AC97 regs */
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#define LS2H_AC97_REG_BASE (LS2H_IO_REG_BASE + 0x00ed0000)
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/* NAND regs */
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#define LS2H_NAND_REG_BASE (LS2H_IO_REG_BASE + 0x00ee0000)
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#define LS2H_NAND_CMD_REG (LS2H_NAND_REG_BASE + 0x0000)
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#define LS2H_NAND_ADDR_C_REG (LS2H_NAND_REG_BASE + 0x0004)
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#define LS2H_NAND_ADDR_R_REG (LS2H_NAND_REG_BASE + 0x0008)
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#define LS2H_NAND_TIMING_REG (LS2H_NAND_REG_BASE + 0x000c)
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#define LS2H_NAND_IDL_REG (LS2H_NAND_REG_BASE + 0x0010)
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#define LS2H_NAND_STA_IDH_REG (LS2H_NAND_REG_BASE + 0x0014)
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#define LS2H_NAND_PARAM_REG (LS2H_NAND_REG_BASE + 0x0018)
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#define LS2H_NAND_OP_NUM_REG (LS2H_NAND_REG_BASE + 0x001c)
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#define LS2H_NAND_CSRDY_MAP_REG (LS2H_NAND_REG_BASE + 0x0020)
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#define LS2H_NAND_DMA_ACC_REG (LS2H_NAND_REG_BASE + 0x0040)
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/* ACPI regs */
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#define LS2H_ACPI_REG_BASE (LS2H_IO_REG_BASE + 0x00ef0000)
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#define LS2H_PM_SOC_REG (LS2H_ACPI_REG_BASE + 0x0000)
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#define LS2H_PM_RESUME_REG (LS2H_ACPI_REG_BASE + 0x0004)
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#define LS2H_PM_RTC_REG (LS2H_ACPI_REG_BASE + 0x0008)
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#define LS2H_PM1_STS_REG (LS2H_ACPI_REG_BASE + 0x000c)
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#define LS2H_PM1_EN_REG (LS2H_ACPI_REG_BASE + 0x0010)
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#define LS2H_PM1_CNT_REG (LS2H_ACPI_REG_BASE + 0x0014)
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#define LS2H_PM1_TMR_REG (LS2H_ACPI_REG_BASE + 0x0018)
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#define LS2H_P_CNT_REG (LS2H_ACPI_REG_BASE + 0x001c)
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#define LS2H_P_LVL2_REG (LS2H_ACPI_REG_BASE + 0x0020)
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#define LS2H_P_LVL3_REG (LS2H_ACPI_REG_BASE + 0x0024)
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#define LS2H_GPE0_STS_REG (LS2H_ACPI_REG_BASE + 0x0028)
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#define LS2H_GPE0_EN_REG (LS2H_ACPI_REG_BASE + 0x002c)
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#define LS2H_RST_CNT_REG (LS2H_ACPI_REG_BASE + 0x0030)
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#define LS2H_WD_SET_REG (LS2H_ACPI_REG_BASE + 0x0034)
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#define LS2H_WD_TIMER_REG (LS2H_ACPI_REG_BASE + 0x0038)
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#define LS2H_DVFS_CNT_REG (LS2H_ACPI_REG_BASE + 0x003c)
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#define LS2H_DVFS_STS_REG (LS2H_ACPI_REG_BASE + 0x0040)
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#define LS2H_MS_CNT_REG (LS2H_ACPI_REG_BASE + 0x0044)
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#define LS2H_MS_THT_REG (LS2H_ACPI_REG_BASE + 0x0048)
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#define LS2H_THSENS_CNT_REG (LS2H_ACPI_REG_BASE + 0x004c)
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#define LS2H_GEN_RTC1_REG (LS2H_ACPI_REG_BASE + 0x0050)
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#define LS2H_GEN_RTC2_REG (LS2H_ACPI_REG_BASE + 0x0054)
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/* RTC regs */
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#define LS2H_RTC_REG_BASE (LS2H_IO_REG_BASE + 0x00ef8000)
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#define LS2H_TOY_TRIM_REG (LS2H_RTC_REG_BASE + 0x0020)
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#define LS2H_TOY_WRITE0_REG (LS2H_RTC_REG_BASE + 0x0024)
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#define LS2H_TOY_WRITE1_REG (LS2H_RTC_REG_BASE + 0x0028)
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#define LS2H_TOY_READ0_REG (LS2H_RTC_REG_BASE + 0x002c)
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#define LS2H_TOY_READ1_REG (LS2H_RTC_REG_BASE + 0x0030)
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#define LS2H_TOY_MATCH0_REG (LS2H_RTC_REG_BASE + 0x0034)
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#define LS2H_TOY_MATCH1_REG (LS2H_RTC_REG_BASE + 0x0038)
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#define LS2H_TOY_MATCH2_REG (LS2H_RTC_REG_BASE + 0x003c)
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#define LS2H_RTC_CTRL_REG (LS2H_RTC_REG_BASE + 0x0040)
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#define LS2H_RTC_TRIM_REG (LS2H_RTC_REG_BASE + 0x0060)
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#define LS2H_RTC_WRITE0_REG (LS2H_RTC_REG_BASE + 0x0064)
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#define LS2H_RTC_READ0_REG (LS2H_RTC_REG_BASE + 0x0068)
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#define LS2H_RTC_MATCH0_REG (LS2H_RTC_REG_BASE + 0x006c)
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#define LS2H_RTC_MATCH1_REG (LS2H_RTC_REG_BASE + 0x0070)
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#define LS2H_RTC_MATCH2_REG (LS2H_RTC_REG_BASE + 0x0074)
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/* LPC regs */
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#define LS2H_LPC_IO_BASE (LS2H_IO_REG_BASE + 0x00f00000)
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#define LS2H_LPC_REG_BASE (LS2H_IO_REG_BASE + 0x00f10000)
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#define LS2H_LPC_CFG0_REG (LS2H_LPC_REG_BASE + 0x0)
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#define LS2H_LPC_CFG1_REG (LS2H_LPC_REG_BASE + 0x4)
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#define LS2H_LPC_CFG2_REG (LS2H_LPC_REG_BASE + 0x8)
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#define LS2H_LPC_CFG3_REG (LS2H_LPC_REG_BASE + 0xc)
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#define LS2H_PCIE_MAX_PORTNUM 3
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#define LS2H_PCIE_PORT0 0
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#define LS2H_PCIE_PORT1 1
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#define LS2H_PCIE_PORT2 2
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#define LS2H_PCIE_PORT3 3
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#define LS2H_PCIE_GET_PORTNUM(sysdata) \
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((((struct pci_controller *)(sysdata))->mem_resource->start \
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& ~LS2H_PCIE_MEM0_DOWN_MASK) >> 25)
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#define LS2H_CHIP_CFG_REG_CLK_CTRL3 0x22c
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#define LS2H_CLK_CTRL3_BIT_PEREF_EN(portnum) (1 << (24 + portnum))
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#define LS2H_PCIE_MEM0_BASE_PORT(portnum) (0x10000000 + (portnum << 25))
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#define LS2H_PCIE_IO_BASE_PORT(portnum) (0x18100000 + (portnum << 22))
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#define LS2H_PCIE_REG_BASE_PORT(portnum) (0x18118000 + (portnum << 22))
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#define LS2H_PCIE_PORT_REG_CTR0 0x0
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#define LS2H_PCIE_REG_CTR0_BIT_LTSSM_EN (1 << 3)
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#define LS2H_PCIE_REG_CTR0_BIT_REQ_L1 (1 << 12)
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#define LS2H_PCIE_REG_CTR0_BIT_RDY_L23 (1 << 13)
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#define LS2H_PCIE_PORT_REG_STAT1 0xC
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#define LS2H_PCIE_REG_STAT1_MASK_LTSSM 0x0000003f
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#define LS2H_PCIE_REG_STAT1_BIT_LINKUP (1 << 6)
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#define LS2H_PCIE_PORT_REG_CFGADDR 0x24
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#define LS2H_PCIE_PORT_REG_CTR_STAT 0x28
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#define LS2H_PCIE_REG_CTR_STAT_BIT_ISX4 (1 << 26)
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#define LS2H_PCIE_REG_CTR_STAT_BIT_ISRC (1 << 27)
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#define LS2H_PCIE_PORT_HEAD_BASE_PORT(portnum) (0x18114000 + (portnum << 22))
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#define LS2H_PCIE_DEV_HEAD_BASE_PORT(portnum) (0x18116000 + (portnum << 22))
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#define LIE_IN_WINDOW(addr,base,mask) ((addr & mask) == base)
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#define MAP_2_WINDOW(addr,mmap,mask) ((addr & (~(mask))) | (mmap & mask))
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#define LS2H_PCIE_MEM0_DOWN_BASE 0x10000000
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#define LS2H_PCIE_MEM0_DOWN_MASK 0xf8000000
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#define LS2H_PCIE_MEM0_UP_BASE 0x10000000
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#define LS2H_PCIE_MEM0_UP_MASK 0xfe000000
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#define LS2H_PCIE_IO_DOWN_BASE 0x18100000
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#define LS2H_PCIE_IO_DOWN_MASK 0xff3f0000
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#define LS2H_PCIE_IO_UP_BASE 0x0
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#define LS2H_PCIE_IO_UP_MASK 0xffff0000
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#endif /*_LS2H_H*/
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