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128 lines
3.8 KiB
128 lines
3.8 KiB
#include "sb700.h"
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#include "rs780_cmn.h"
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static void usb_init(device_t dev)
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{
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u8 byte;
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u16 word;
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u32 dword;
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device_t sm_dev;
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//lycheng do in tgt_devinit()
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#if 1
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/* Enable OHCI0-4 and EHCI Controllers */
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printk_info("Enable OHCI0-4 and EHCI Controllers\n");
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//sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
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sm_dev = _pci_make_tag(0, 0x14, 0);
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byte = pci_read_config8(sm_dev, 0x68);
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//byte |= 0x3F;
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byte |= 0xFF;
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pci_write_config8(sm_dev, 0x68, byte);
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#endif
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#if 1
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/* RPR 5.2 Enables the USB PME Event,Enable USB resume support */
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byte = pm_ioread(0x61);
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byte |= 1 << 6;
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pm_iowrite(0x61, byte);
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byte = pm_ioread(0x65);
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byte |= 1 << 2;
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pm_iowrite(0x65, byte);
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/* RPR 5.3 Support USB device wakeup from the S4/S5 state */
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byte = pm_ioread(0x65);
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byte &= ~(1 << 0);
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pm_iowrite(0x65, byte);
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/* RPR 5.6 Enable the USB controller to get reset by any software that generate a PCIRst# condition */
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byte = pm_ioread(0x65);
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byte |= (1 << 4);
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pm_iowrite(0x65, byte);
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#endif
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/* RPR 5.11 Disable OHCI MSI Capability */
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printk_info("Disable OHCI MSI Capability\n");
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word = pci_read_config16(dev, 0x40);
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//word |= (0x1F << 8);
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word |= (0x3 << 8);
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pci_write_config16(dev, 0x40, word);
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/* RPR 5.8 Disable the OHCI Dynamic Power Saving feature */
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printk("Disable the OHCI Dynamic Power Saving feature\n");
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dword = pci_read_config32(dev, 0x50);
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//dword &= ~(1 << 16);
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dword |= (1 << 31);
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pci_write_config32(dev, 0x50, dword);
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#if 0
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/* Set a default latency timer. */
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pci_write_config8(dev, 0x0d, 0x40); //PCI_LATENCY_TIMER
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byte = pci_read_config8(dev, 0x3d); //PCI_INTERRUPT_PIN
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if (byte) {
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pci_write_config8(dev, 0x3c, 0); //PCI_INTERRUPT_LINE
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}
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/* Set the cache line size, so far 64 bytes is good for everyone. */
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pci_write_config8(dev, 0x0c, 64 >> 2); //PCI_CACHE_LINE_SIZE
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/*enable io/memory space*/
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pci_write_config8(dev, 0x04, (1<<0|1<<1|1<<2));
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#endif
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}
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static void usb_init2(device_t dev)
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{
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u8 byte;
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u16 word;
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u32 dword;
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u8 *usb2_bar0;
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/* dword = pci_read_config32(dev, 0xf8); */
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/* dword |= 40; */
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/* pci_write_config32(dev, 0xf8, dword); */
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#if 1 //because of disable usb, lycheng
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usb2_bar0 = (u8 *) (pci_read_config32(dev, 0x10) & ~0xFF);
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printk_info("usb2_bar0=%p\n", usb2_bar0);
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/* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */
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dword = 0x00020F00;
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WRITEL(dword, usb2_bar0 + 0xC0);
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/* RPR5.5 Sets In/OUT FIFO threshold for best performance */
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//dword = 0x00200040;
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dword = 0x00400040;
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WRITEL(dword, usb2_bar0 + 0xA4);
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#endif
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/* RPR6.11 Disabling EHCI Advance Asynchronous Enhancement */
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printk_info("Disabling EHCI Advance Asynchronous Enhancement\n");
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dword = pci_read_config32(dev, 0x50);
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dword |= (1 << 28);
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pci_write_config32(dev, 0x50, dword);
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/* RPR6.15 EHCI Async Park Mode */
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printk_info("EHCI Async Park Mode\n");
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dword = pci_read_config32(dev, 0x50);
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dword |= (1 << 23);
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pci_write_config32(dev, 0x50, dword);
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/* RPR5.10 Disable EHCI MSI support */
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printk_info("Disable EHCI MSI support\n");
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byte = pci_read_config8(dev, 0x50);
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byte |= (1 << 6);
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pci_write_config8(dev, 0x50, byte);
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#if 1 //because of disable usb, lycheng
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/* RPR6.17 Disable the EHCI Dynamic Power Saving feature */
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word = READL(usb2_bar0 + 0xBC);
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word &= ~(1 << 12);
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WRITEW(word, usb2_bar0 + 0xBC);
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#endif
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/* Set a default latency timer. */
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pci_write_config8(dev, 0x0d, 0x40); //PCI_LATENCY_TIMER
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byte = pci_read_config8(dev, 0x3d); //PCI_INTERRUPT_PIN
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if (byte) {
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pci_write_config8(dev, 0x3c, 0); //PCI_INTERRUPT_LINE
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}
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/* Set the cache line size, so far 64 bytes is good for everyone. */
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pci_write_config8(dev, 0x0c, 64 >> 2); //PCI_CACHE_LINE_SIZE
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/*enable io/memory space*/
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pci_write_config8(dev, 0x04, (1<<0|1<<1|1<<2));
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}
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