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166 lines
5.3 KiB
166 lines
5.3 KiB
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __RS780_H__
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#define __RS780_H__
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#include <time.h>
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#include "sb700.h"
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#define NBMISC_INDEX 0x60
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#define NBHTIU_INDEX 0xA8
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#define NBMC_INDEX 0xE8
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#define NBPCIE_INDEX 0xE0
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#define EXT_CONF_BASE_ADDRESS 0x17000000
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#define TEMP_MMIO_BASE_ADDRESS 0xC0000000
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typedef struct __PCIE_CFG__ {
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u16 Config;
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u8 ResetReleaseDelay;
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u8 Gfx0Width;
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u8 Gfx1Width;
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u8 GfxPayload;
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u8 GppPayload;
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u8 PortDetect;
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u8 PortHp; /* hot plug */
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u16 DbgConfig;
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u32 DbgConfig2;
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u8 GfxLx;
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u8 GppLx;
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u8 NBSBLx;
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u8 PortSlotInit;
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u8 Gfx0Pwr;
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u8 Gfx1Pwr;
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u8 GppPwr;
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} PCIE_CFG;
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/* PCIE config flags */
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#define PCIE_DUALSLOT_CONFIG (1 << 0)
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#define PCIE_OVERCLOCK_ENABLE (1 << 1)
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#define PCIE_GPP_CLK_GATING (1 << 2)
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#define PCIE_ENABLE_STATIC_DEV_REMAP (1 << 3)
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#define PCIE_OFF_UNUSED_GFX_LANES (1 << 4)
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#define PCIE_OFF_UNUSED_GPP_LANES (1 << 5)
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#define PCIE_DISABLE_HIDE_UNUSED_PORTS (1 << 7)
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#define PCIE_GFX_CLK_GATING (1 << 11)
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#define PCIE_GFX_COMPLIANCE (1 << 14)
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#define PCIE_GPP_COMPLIANCE (1 << 15)
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typedef enum _NB_REVISION_ {
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REV_RS780_A11 = 5,
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REV_RS780_A12 = 6,
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REV_RS780_A21 = 7,
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} NB_REVISION;
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#define PCI_ADDR(BUS, DEV, FN, WHERE) ( \
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(((BUS) & 0xFF) << 16) | \
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(((DEV) & 0x1f) << 11) | \
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(((FN) & 0x07) << 8) | \
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((WHERE) & 0xFF))
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#define PCI_DEV(BUS, DEV, FN) ( \
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(((BUS) & 0xFF) << 16) | \
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(((DEV) & 0x1f) << 11) | \
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(((FN) & 0x7) << 8))
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/* -------------------- ----------------------
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* NBMISCIND
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------------------- -----------------------*/
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#define PCIE_LINK_CFG 0x8
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#define PCIE_NBCFG_REG7 0x37
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#define STRAPS_OUTPUT_MUX_7 0x67
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#define STRAPS_OUTPUT_MUX_A 0x6a
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/* -------------------- ----------------------
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* PCIEIND
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------------------- -----------------------*/
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#define PCIE_CI_CNTL 0x20
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#define PCIE_LC_LINK_WIDTH 0xa2
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#define PCIE_LC_STATE0 0xa5
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//#define PCIE_VC0_RESOURCE_STATUS 0x11a /* 16bit read only */
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#define PCIE_VC0_RESOURCE_STATUS 0x12a /* 16bit read only */
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#define PCIE_CORE_INDEX_GFX (0 << 16) /* see 5.2.2 */
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#define PCIE_CORE_INDEX_GPPSB (1 << 16)
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//add for rs780
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#define PCIE_CORE_INDEX_GPP (0x02 << 16)
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#define PCIE_CORE_INDEX_BRDCST (0x03 << 16)
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/* contents of PCIE_NBCFG_REG7 */
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#define RECONFIG_GPPSB_EN (1 << 12)
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#define RECONFIG_GPPSB_GPPSB (1 << 14)
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#define RECONFIG_GPPSB_LINK_CONFIG (1 << 15)
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#define RECONFIG_GPPSB_ATOMIC_RESET (1 << 17)
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/* contents of PCIE_VC0_RESOURCE_STATUS */
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#define VC_NEGOTIATION_PENDING (1 << 1)
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#define LC_STATE_RECONFIG_GPPSB 0x10
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/* ------------------------------------------------
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* Global variable
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* ------------------------------------------------- */
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extern PCIE_CFG AtiPcieCfg;
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/* ----------------- export funtions ----------------- */
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u32 nbmisc_read_index(device_t nb_dev, u32 index);
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void nbmisc_write_index(device_t nb_dev, u32 index, u32 data);
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u32 nbpcie_p_read_index(device_t dev, u32 index);
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void nbpcie_p_write_index(device_t dev, u32 index, u32 data);
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u32 nbpcie_ind_read_index(device_t nb_dev, u32 index);
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void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data);
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u32 htiu_read_index(device_t nb_dev, u32 index);
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void htiu_write_index(device_t nb_dev, u32 index, u32 data);
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u32 nbmc_read_index(device_t nb_dev, u32 index);
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void nbmc_write_index(device_t nb_dev, u32 index, u32 data);
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#if 0
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u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg);
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void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg, u32 mask, u32 val);
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#endif
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u16 pci_ext_read_config16(device_t nb_dev, device_t dev, u32 reg);
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void pci_ext_write_config16(device_t nb_dev, device_t dev, u32 reg, u32 mask, u32 val);
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void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);
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void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, u8 val);
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void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);
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void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);
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void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);
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void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val);
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void rs780_set_tom(device_t nb_dev);
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void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add);
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void enable_pcie_bar3(device_t nb_dev);
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void disable_pcie_bar3(device_t nb_dev);
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void rs780_enable(device_t dev);
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void rs780_gpp_sb_init(device_t nb_dev, device_t dev, u32 port);
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void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port);
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void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev);
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void config_gpp_core(device_t nb_dev, device_t sb_dev);
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void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port);
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u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port);
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#endif /* RS780_H */
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