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254 lines
7.1 KiB
254 lines
7.1 KiB
#include "sb700.h"
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#include "rs780_cmn.h"
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#include "sb700_smbus.c"
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/*
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* SB600 enables all USB controllers by default in SMBUS Control.
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* SB600 enables SATA by default in SMBUS Control.
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*/
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static void sm_init(device_t dev)
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{
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u8 byte;
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u8 byte_old;
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u32 dword;
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u32 ioapic_base;
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u32 on;
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u32 nmi_option;
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printk_info("sm_init().\n");
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//ioapic_base = pci_read_config32(dev, 0x74) & (0xffffffe0); /* some like mem resource, but does not have enable bit */
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//setup_ioapic(ioapic_base);
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dword = pci_read_config8(dev, 0x62);
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dword |= 1 << 2;
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pci_write_config8(dev, 0x62, dword);
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printk_info("enable 0xCD6 0xCD7\n");
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dword = pci_read_config32(dev, 0x78);
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dword |= 1 << 9;
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pci_write_config32(dev, 0x78, dword); /* enable 0xCD6 0xCD7 */
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#if 0
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//add by lycheng
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printk_info("clear sata and ide controller into combined mode\n");
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printk_info("PATA is primary\n");
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dword = pci_read_config32(dev, 0xAD);
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dword |= (1 << 4);
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dword &= ~(1 << 3);
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pci_write_config32(dev, 0xAD, dword);
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#endif
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/* bit 10: MultiMediaTimerIrqEn */
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printk_info("MultiMediaTimerIrqEn\n");
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dword = pci_read_config8(dev, 0x64);
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dword |= 1 << 10;
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pci_write_config8(dev, 0x64, dword);
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/* enable serial irq */
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printk_info("enable serial irq\n");
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byte = pci_read_config8(dev, 0x69);
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byte |= 1 << 7; /* enable serial irq function */
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byte &= ~(0xF << 2);
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byte |= 4 << 2; /* set NumSerIrqBits=4 */
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pci_write_config8(dev, 0x69, byte);
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#if 1
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printk_info("Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7\n");
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byte = pm_ioread(0x61);
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byte |= 1 << 1; /* Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7 */
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pm_iowrite(0x61, byte);
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/* disable SMI */
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printk_info("disable SMI\n");
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byte = pm_ioread(0x53);
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byte |= 1 << 3;
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pm_iowrite(0x53, byte);
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/* power after power fail */
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//on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
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//get_option(&on, "power_on_after_fail");
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printk_info("power after power fail\n");
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on = 0;
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byte = pm_ioread(0x74);
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byte &= ~0x03;
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if (on) {
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byte |= 2;
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}
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byte |= 1 << 2;
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pm_iowrite(0x74, byte);
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printk_info("set power %s after power fail\n", on ? "on" : "off");
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#endif
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#if 1
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printk_info("1\n");
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byte = pm_ioread(0x68);
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byte &= ~(1 << 1);
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/* 2.6 */
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byte |= 1 << 2;
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pm_iowrite(0x68, byte);
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/* 2.6 */
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printk_info("2\n");
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byte = pm_ioread(0x65);
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byte &= ~(1 << 7);
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pm_iowrite(0x65, byte);
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#endif
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#if 1
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/* 2.16 */
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printk_info("2.16\n");
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byte = pm_ioread(0x55);
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byte |= 1 << 5;
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pm_iowrite(0x55, byte);
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byte = pm_ioread(0xD7);
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byte |= 1 << 6 | 1 << 1;;
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pm_iowrite(0xD7, byte);
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/* 2.15 */
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printk_info("2.15\n");
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byte = pm_ioread(0x42);
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byte &= ~(1 << 2);
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pm_iowrite(0x42, byte);
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#if 0
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/* Set up NMI on errors */
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printk_info("set up NMI on errors\n");
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byte = INB(0xba000070); /* RTC70 */
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byte_old = byte;
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//nmi_option = NMI_OFF;
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nmi_option = 0;
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//get_option(&nmi_option, "nmi");
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if (nmi_option) {
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byte &= ~(1 << 7); /* set NMI */
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printk_info("++++++++++set NMI+++++\n");
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} else {
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byte |= (1 << 7); /* Can not mask NMI from PCI-E and NMI_NOW */
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printk_info("++++++++++no set NMI+++++\n");
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}
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byte &= ~(1 << 7);
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if (byte != byte_old) {
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OUTB(byte, 0xba000070);
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}
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#endif
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#endif
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/* 2.10 IO Trap Settings */
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//try move later
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printk_info("IO Trap Setting\n");
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abcfg_reg(0x10090, 1 << 16, 1 << 16);
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/* ab index */
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printk_info("ab index\n");
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//pci_write_config32(dev, 0xF0, AB_INDX);
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pci_write_config32(dev, 0xF0, 0x00000cd8);
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/* Initialize the real time clock */
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//rtc_init(0);
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/* 4.3 Enabling Upstream DMA Access */
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printk_info("Enabling Upstream DMA Access\n");
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axcfg_reg(0x04, 1 << 2, 1 << 2); //780
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/*3.4 Enabling IDE/PCIB Prefetch for Performance Enhancement */
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printk_info("Enabling IDE/PCIB Prefetch for Performance Enhancement\n");
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abcfg_reg(0x10060, 9 << 17, 9 << 17);
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abcfg_reg(0x10064, 9 << 17, 9 << 17);
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/* 3.5 Enabling OHCI Prefetch for Performance Enhancement */
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printk_info("Enabling OHCI Prefetch for Performance Enhancement\n");
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abcfg_reg(0x80, 1 << 0, 1<< 0);
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/* 3.6 B-Link Client's Credit Variable Settings for the Downstream Arbitration Equation */
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/* 3.7 Enabling Additional Address Bits Checking in Downstream */
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//abcfg_reg(0x9c, 3 << 0, 3 << 0);
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printk_info("Enabling Additional Address Bits Checking in Downstream\n");
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abcfg_reg(0x9c, 3 << 0 | 1 << 8, 3 << 0 | 1 << 8);
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/* 3.8 Set B-Link Prefetch Mode */
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printk_info("Set B-Link Prefetch Mode\n");
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abcfg_reg(0x80, 3 << 1, 3 << 1);
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/* 3.9 Enabling Detection of Upstream Interrupts */
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printk_info("Enabling Detection of Upstream Interrupts\n");
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abcfg_reg(0x94, 1 << 20 | 0x7FFFF,1 << 20 | 0x00FEE);
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/* 3.10: Enabling Downstream Posted Transactions to Pass Non-Posted
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* Transactions for the K8 Platform (for All Revisions) */
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printk_info("Enabling Downstream Posted Transactions to Pass Non-Posted\n");
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//try
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abcfg_reg(0x10090, 1 << 8, 1 << 8);
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/* 3.11:Programming Cycle Delay for AB and BIF Clock Gating */
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/* 3.12: Enabling AB and BIF Clock Gating */
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abcfg_reg(0x10054, 0xFFFF0000, 0x1040000);
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abcfg_reg(0x54, 0xFF << 16, 4 << 16);
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printk_info("3.11, ABCFG:0x54\n");
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abcfg_reg(0x54, 1 << 24, 1 << 24);
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printk_info("3.12, ABCFG:0x54\n");
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abcfg_reg(0x98, 0x0000FF00, 0x00004700);
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#if 0
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//lycheng
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abcfg_reg(0x10056, 0xFF << 0, 4 << 0);
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printk_info("3.11, ABCFG:0x10056\n");
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abcfg_reg(0x10056, 1 << 8, 1 << 8);
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printk_info("Set A-Link Prefetch Mode\n");
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abcfg_reg(0x1006c, 3 << 1, 3 << 1);
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axindxc_reg(0x10, 9 << 1, 9 << 1);
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axindxc_reg(0x21, 1 << 0, 1 << 0);
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abcfg_reg(0x10050, 1 << 2, 1 << 2);
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//end
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#endif
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/* 4.13:Enabling AB Int_Arbiter Enhancement (for All Revisions) */
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printk_info("Enabling AB Int_Arbiter Enhancement\n");
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abcfg_reg(0x10054, 0x0000FFFF, 0x07FF);
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#if 1
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/* 4.14:Enabling Requester ID for upstream traffic. */
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printk_info("Enabling Requester ID for upstream traffic\n");
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abcfg_reg(0x98, 1 << 16, 0 << 16);
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#endif
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#if 1
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/* 9.2: Enableing IDE Data Bus DD7 Pull Down Resistor */
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printk_info("Enableing IDE Data Bus DD7 Pull Down Resistor\n");
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byte = pm2_ioread(0xE5);
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byte |= 1 << 2;
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pm2_iowrite(0xE5, byte);
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/* Enable IDE controller. */
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printk_info("Enable IDE controller.\n");
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byte = pm_ioread(0x59);
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byte &= ~(1 << 1);
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pm_iowrite(0x59, byte);
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#endif
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#if 1
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/* Enable NbSb virtual channel */
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printk_info("Enable NbSb virtual channel\n");
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axcfg_reg(0x114, 0x3f << 1, 0 << 1);
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axcfg_reg(0x120, 0x7f << 1, 0x7f << 1);
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axcfg_reg(0x120, 7 << 24, 1 << 24);
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axcfg_reg(0x120, 1 << 31, 1 << 31);
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abcfg_reg(0x50, 1 << 3, 1 << 3);
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#endif
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//lycheng for debug 8259 interrupt
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#if 0
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printk_info("Shadow PIC register enable\n");
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dword = pci_read_config32(dev, 0x48);
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dword |= 1 << 23;
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pci_write_config32(dev, 0x48, dword);
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#endif
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printk_info("K8 INTR enable\n");
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dword = pci_read_config32(dev, 0x60);
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dword |= 1 << 19;
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pci_write_config32(dev, 0x60, dword);
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printk_info("Features enable\n");
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dword = pci_read_config32(dev, 0x64);
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dword |= ((1 << 0));
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dword &= ~((1 << 3)|(1 << 7));
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pci_write_config32(dev, 0x64, dword);
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printk_info("INTAFix\n");
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dword = pci_read_config32(dev, 0xe0);
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dword |= 1 << 11;
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pci_write_config32(dev, 0xe0, dword);
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//end lycheng
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printk_info("sm_init() end\n");
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}
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