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133 lines
2.1 KiB
133 lines
2.1 KiB
/*************************
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* just suport ls3a2h
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*************************/
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#define i2c_wait \
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li v0, LS2H_I2C0_CR_REG; \
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11:; \
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lb v1, 0x0(v0); \
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li v1, CR_TIP; \
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bne v1, 11b; \
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nop
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LEAF(i2cinit)
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li v1, 0x2c
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li v0, LS2H_I2C0_PRER_LO_REG
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sb v1, 0x0(v0)
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li v1, 0x01
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li v0, LS2H_I2C0_PRER_HI_REG
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sb v1, 0x0(v0)
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li v1, 0x80
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li v0, LS2H_I2C0_CTR_REG
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sb v1, 0x0(v0)
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jr ra
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nop
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END(i2cinit)
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LEAF(i2cread)
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/*
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* use register:
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* v0, v1
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* a0, a1
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* input: a0,a1
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* a0: device ID
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* a1: register offset
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* v0: return value
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*
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*/
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/*i2c_send_b*/
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/* load device address */
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andi v1, a0, 0xfe
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li v0, LS2H_I2C0_TXR_REG
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sb v1, 0x0(v0)
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/* send start frame */
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li v1, CR_START | CR_WRITE
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li v0, LS2H_I2C0_CR_REG
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sb v1, 0x0(v0)
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/* waite send finished */
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// i2c_wait_tip
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li v0, LS2H_I2C0_SR_REG
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1:
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lb v1, 0x0(v0)
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andi v1, v1, SR_TIP
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bnez v1, 1b
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nop
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/* load data to be send */
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move v1, a1
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li v0, LS2H_I2C0_TXR_REG
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sb v1, 0x0(v0)
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/* send data frame */
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li v1, CR_WRITE
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li v0, LS2H_I2C0_CR_REG
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sb v1, 0x0(v0)
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/* waite send finished */
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// i2c_wait_tip
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li v0, LS2H_I2C0_SR_REG
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1:
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lb v1, 0x0(v0)
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andi v1, v1, SR_TIP
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bnez v1, 1b
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nop
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/* i2c_read_b */
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/* load device address */
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ori v1, a0, 0x1
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li v0, LS2H_I2C0_TXR_REG
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sb v1, 0x0(v0)
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/* send start frame */
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li v1, CR_START | CR_WRITE
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li v0, LS2H_I2C0_CR_REG
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sb v1, 0x0(v0)
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/* waite send finished */
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// i2c_wait_tip
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li v0, LS2H_I2C0_SR_REG
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1:
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lb v1, 0x0(v0)
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andi v1, v1, SR_TIP
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bnez v1, 1b
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nop
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/* receive data to fifo */
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li v1, CR_READ | CR_ACK
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li v0, LS2H_I2C0_CR_REG
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sb v1, 0x0(v0)
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// i2c_wait_tip
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li v0, LS2H_I2C0_SR_REG
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1:
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lb v1, 0x0(v0)
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andi v1, v1, SR_TIP
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bnez v1, 1b
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nop
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/* read data from fifo */
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li v0, LS2H_I2C0_RXR_REG
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lb a1, 0x0(v0)
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/* i2c_stop */
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/* free i2c bus */
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li v0, LS2H_I2C0_CR_REG
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li v1, CR_STOP
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sb v1, 0x0(v0)
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1:
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li v0, LS2H_I2C0_SR_REG
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lb v1, 0x0(v0)
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andi v1, v1, SR_BUSY
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bnez v1, 1b
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nop
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move v0, a1
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jr ra
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nop
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END(i2cread)
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