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1249 lines
20 KiB
1249 lines
20 KiB
/*whd : loongson3_HT_init.S
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used to set up the HyperTransport interface
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and the South bridge
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mainly for MCP68
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*/
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######################################################
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#define HT_32bit_TRANS
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#define WITH_HT
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//#define HT_800M
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//#define HT_16bit
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//#define HT_RECONNECT
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#define HT_REG_TRANS
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######################################################
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#ifdef HT_32bit_TRANS //PCI CFG : TYPE 0:
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TTYDBG("32 bit PCI space translate to 64 bit HT space\r\n")
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dli t0, 0x900000003ff02000
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dli t2, 0x900000003ff02400
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1:
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//map HT: PCI IO : 0x90000efd_fc000000 --> 0x18000000
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//map 0x90000efd_fd000000 --> 0x19000000
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//map HT: PCI CFG: 0x90000efd_fe000000 --> 0x1a000000
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//map HT: PCI CFG: 0x90000efd_ff000000 --> 0x1b000000
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dli t1, 0x0000000018000000
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sd t1, 0x0(t0)
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dli t1, 0xfffffffffc000000
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sd t1, 0x40(t0)
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dli t1, 0x00000efdfc0000f7
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sd t1, 0x80(t0)
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//HT Space enable
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//map 0x90000e00_00000000 --> 0x90000e00_00000000
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dli t1, 0x00000e0000000000
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sd t1, 0x8(t0)
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dli t1, 0xffffff0000000000
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sd t1, 0x48(t0)
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dli t1, 0x00000e00000000f7
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sd t1, 0x88(t0)
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//HT: PCI LO BASE
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//map 0x90000e00_00000000 --> 0x10000000
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dli t1, 0x0000000010000000
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sd t1, 0x10(t0)
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dli t1, 0xfffffffffc000000
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sd t1, 0x50(t0)
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dli t1, 0x00000e00000000f7
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sd t1, 0x90(t0)
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//HT: PCI HI BASE
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//map 0x90000e00_10000000 --> 0x10000000
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dli t1, 0x0000000010000000
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sd t1, 0x18(t0)
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dli t1, 0xfffffffff8000000
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sd t1, 0x58(t0)
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dli t1, 0x00000e00100000f7
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sd t1, 0x98(t0)
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#ifdef HT_REG_TRANS
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//HT REG BASE
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//map 0x90000efd_fb000000 --> 0x1e000000
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dli t1, 0x000000001e000000
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sd t1, 0x20(t0)
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dli t1, 0xffffffffff000000
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sd t1, 0x60(t0)
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dli t1, 0x00000efdfb0000f7
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sd t1, 0xa0(t0)
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#endif
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daddiu t0, t0, 0x100
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bne t0, t2, 1b
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nop
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#endif
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//////////////////
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#if 0
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TTYDBG("DEBUG......\r\n")
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dli t0, 0x900000003ff02000
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dli t1, 0x900000003ff02400
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1 :
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ld a0, 0(t0)
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dsrl a0, 32
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bal hexserial
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nop
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ld a0, 0(t0)
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bal hexserial
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nop
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TTYDBG("\r\n")
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daddiu t0, t0, 8
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nop
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bne t0, t1, 1b
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nop
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TTYDBG("DEBUG END......\r\n")
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#endif
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#if 0//Print all HT registers
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TTYDBG("Print all HT registers\r\n")
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dli t2, 0x90000efdfb000000
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dli t3, 0x90000efdfb000100
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1:
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lw a0, 0x00(t2)
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bal hexserial
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nop
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TTYDBG("\r\n")
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daddi t2, t2, 0x4
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bne t2, t3, 1b
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nop
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#endif
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#ifdef WITH_HT
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#if 1//wait until HT link up
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TTYDBG("Waiting HyperTransport bus to be up.")
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dli t0, 0x90000efdfb000000
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li t1, 0x1f
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1:
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lw a0, 0x44(t0)
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#bal hexserial
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nop
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beqz t1,2f
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nop
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TTYDBG(">")
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addi t1, t1, -1
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b 3f
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nop
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2:
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TTYDBG("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b=")
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li t1, 0x1f
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3:
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lw a0, 0x44(t0)
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li a1, 0x20
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and a0, a0, a1
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beqz a0, 1b
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nop
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TTYDBG("\r\n")
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lw a0, 0x44(t0)
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bal hexserial
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nop
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TTYDBG("\r\n")
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#endif
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#if 0
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TTYDBG("HT bus 0 scanning with deviceID and vendorID\r\n")
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dli t0, 0x90000efdfe000000
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// li t0, 0xbfe80000
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li t3, 32
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1 :
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li t2, 8
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2 :
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// lw a0, 0x0(t0)
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// li a1, 0xffffffff
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// beq a0, a1, ht_next_id
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// nop
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TTYDBG("Device(")
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nop
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li a0, 32
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sub a0, a0, t3
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bal hexserial
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nop
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TTYDBG(")---")
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nop
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TTYDBG("Function(")
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nop
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li a0, 8
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sub a0, a0, t2
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bal hexserial
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nop
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TTYDBG(") : ")
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nop
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lw a0, 0x0(t0)
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bal hexserial
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nop
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TTYDBG("\t")
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nop
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TTYDBG("CAPABILITY POINTER : ")
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lw a0, 0x34(t0)
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bal hexserial
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nop
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TTYDBG("\r\n")
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ht_next_id :
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daddi t0, t0, 0x100
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addi t2, t2, -1
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bnez t2, 2b
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nop
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addi t3, t3, -1
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bnez t3, 1b
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nop
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TTYDBG("END HT bus 0 scan\r\n")
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nop
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#endif
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#if 0//Print all HT registers
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TTYDBG("Print all HT registers\r\n")
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dli t2, 0x90000efdfb000000
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dli t3, 0x90000efdfb000100
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1:
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lw a0, 0x00(t2)
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bal hexserial
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nop
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TTYDBG("\r\n")
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daddi t2, t2, 0x4
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bne t2, t3, 1b
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nop
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#endif
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#if 0//Set HT channel priority
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TTYDBG("Set HT Channel priority\r\n")
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dli t2, 0x90000efdfb000000
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li t0, 0x4f04
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//li t0, 0x4f14
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//li t0, 0x4f44 #45S
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sh t0, 0x50(t2)
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lw a0, 0x50(t2)
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bal hexserial
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nop
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TTYDBG("\r\n")
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#endif
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#if 0//Set HT Seq
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TTYDBG("Don't care about HT Channel seq\r\n")
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dli t2, 0x90000efdfb000000
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lw t0, 0x50(t2)
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li a0, 0x00200000
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or t0, t0, a0
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sw t0, 0x50(t2)
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lw a0, 0x50(t2)
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bal hexserial
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nop
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TTYDBG("\r\n")
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#endif
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#if 0//Set CPU2HT access with seq
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TTYDBG("Set CPU2HT Channel with seq\r\n")
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dli t2, 0x90000efdfb000000
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lw t0, 0x50(t2)
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li a0, 0x00110000
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or t0, t0, a0
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sw t0, 0x50(t2)
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lw a0, 0x50(t2)
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bal hexserial
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nop
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TTYDBG("\r\n")
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#endif
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#if 1//OPEN RX SPACE in HOST
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TTYDBG("HT RX DMA address ENABLE\r\n")
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dli t2, 0x90000efdfb000060
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li t0, 0xc0000000
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sw t0, 0x0(t2)
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li t0, 0x0080ff80
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sw t0, 0x4(t2)
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//TTYDBG("HT RX DMA address ENABLE done 1\r\n")
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//li t0, 0x80000000
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//sw t0, 0x8(t2)
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//li t0, 0x0000ffc0
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//sw t0, 0xc(t2)
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////TTYDBG("HT RX DMA address ENABLE done 2\r\n")
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//li t0, 0xc0000000
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//sw t0, 0x10(t2)
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//li t0, 0xfdfcfffc
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//sw t0, 0x14(t2)
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////TTYDBG("HT RX DMA address ENABLE done 3\r\n")
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#endif
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#if 0//Set Mem space post
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TTYDBG("Set HT Memory space all post\r\n")
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dli t2, 0x90000efdfb000000
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li t0, 0x80000010
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sw t0, 0xd0(t2)
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li t0, 0x0010fff8
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sw t0, 0xd4(t2)
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#endif
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#ifdef HT_16bit//Set HT bridge to be 16-bit width
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TTYDBG("Setting HyperTransport Controller to be 16-bit width\r\n")
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dli t2, 0x90000efdfb000000
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#li t0, 0x10 //RECEIVER 16bit
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li t0, 0x11
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sb t0, 0x47(t2)
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lw a0, 0x44(t2)
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bal hexserial
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nop
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TTYDBG("\r\n")
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#else
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TTYDBG("Setting HyperTransport Controller to be 8-bit width\r\n")
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dli t2, 0x90000efdfb000000
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li t0, 0x00
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sb t0, 0x47(t2)
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lw a0, 0x44(t2)
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bal hexserial
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nop
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TTYDBG("\r\n")
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#endif
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#ifdef HT_800M//Set HT bridge to be 800Mhz
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TTYDBG("Setting HyperTransport Controller to be 800Mhz\r\n")
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dli t2, 0x90000efdfb000000
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#li t0, 0x2 //Frequency: 400 Mhz
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li t0, 0x5 //Frequency: 800 Mhz
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sb t0, 0x49(t2)
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lw a0, 0x48(t2)
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bal hexserial
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nop
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TTYDBG("\r\n")
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#endif
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#endif
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#ifdef WITH_HT
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#if 0//SET RX SPACE UNCACHE
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TTYDBG("HT RX DMA SET to UNCACHE\r\n")
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dli t2, 0x90000efdfb0000f0
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li t0, 0xc0000000
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sw t0, 0x0(t2)
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li t0, 0x0080ff80
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sw t0, 0x4(t2)
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//li t0, 0x80000000
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//sw t0, 0x8(t2)
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//li t0, 0x0000ffc0
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//sw t0, 0xc(t2)
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#endif
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#if 1 //SET HT as HOST
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TTYDBG("SET HT as HOST\r\n")
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dli t2, 0x90000efdfb000040
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lw a0, 0x0(t2)
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bal hexserial
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nop
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li t1, 0xfbffffff
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and a0, a0, t1
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sw a0, 0x0(t2)
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lw a0, 0x0(t2)
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bal hexserial
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nop
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TTYDBG("\r\n")
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#endif
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#if 0
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li t1, 31
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TTYDBG("start HT bus scan\r\n")
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//li t0, 0xba000000
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dli t0, 0x90000efdfe000000
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1:
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move a0, t0
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bal hexserial
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nop
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TTYDBG(" : ")
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lw a0, 0x0(t0)
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bal hexserial
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nop
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TTYDBG("\r\n")
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nop
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//add t0, t0, 0x800
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dadd t0, t0, 0x800
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bnez t1, 1b
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sub t1, t1, 1
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TTYDBG("END HT bus scan\r\n")
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nop
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#endif
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#if 0 //Find capability in DEVICE 0
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TTYDBG("Find capability in DEVICE 1\r\n")
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TTYDBG("function 0\r\n")
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//li t0, 0xba000000
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dli t0, 0x90000efdfe000000
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lb t1, 0x34(t0)
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1:
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TTYDBG("Address of Capability : ")
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move a0, t1
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bal hexserial
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nop
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TTYDBG("\r\n")
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TTYDBG("First Line of Capability : ")
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dadd t1, t1, t0
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lw a0, 0(t1)
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bal hexserial
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nop
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TTYDBG("\r\n")
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#TTYDBG("Second Line of Capability : ")
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#add t1, t1, t0
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#lw a0, 4(t1)
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#bal hexserial
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#nop
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#TTYDBG("\r\n")
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lb t1, 0x1(t1)
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andi t1, t1, 0xff
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bnez t1, 1b
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nop
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/*
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TTYDBG("function 1\r\n")
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//li t0, 0xba000900
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dli t0, 0x90000efdfe000900
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lb t1, 0x34(t0)
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1:
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TTYDBG("Address of Capability : ")
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move a0, t1
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bal hexserial
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nop
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TTYDBG("\r\n")
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TTYDBG("First Line of Capability : ")
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dadd t1, t1, t0
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lw a0, 0(t1)
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bal hexserial
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nop
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TTYDBG("\r\n")
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lb t1, 0x1(t1)
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bnez t1, 1b
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nop
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TTYDBG("function 2\r\n")
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//li t0, 0xba000a00
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dli t0, 0x90000efdfe000a00
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lb t1, 0x34(t0)
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1:
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TTYDBG("Address of Capability : ")
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move a0, t1
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bal hexserial
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nop
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TTYDBG("\r\n")
|
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TTYDBG("First Line of Capability : ")
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dadd t1, t1, t0
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lw a0, 0(t1)
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bal hexserial
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nop
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TTYDBG("\r\n")
|
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lb t1, 0x1(t1)
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bnez t1, 1b
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nop
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TTYDBG("function 3\r\n")
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//li t0, 0xba000b00
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dli t0, 0x90000efdfe000b00
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lb t1, 0x34(t0)
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1:
|
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TTYDBG("Address of Capability : ")
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move a0, t1
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bal hexserial
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nop
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TTYDBG("\r\n")
|
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TTYDBG("First Line of Capability : ")
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add t1, t1, t0
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lw a0, 0(t1)
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bal hexserial
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nop
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TTYDBG("\r\n")
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lb t1, 0x1(t1)
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bnez t1, 1b
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nop
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*/
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|
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TTYDBG("End of Capability\r\n")
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|
|
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li t1, 6
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TTYDBG("start Capability of HT scan\r\n")
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//li t0, 0xba000044
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dli t0, 0x90000efdfe000044
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1:
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move a0, t0
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bal hexserial
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nop
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TTYDBG(" : ")
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lw a0, 0x0(t0)
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bal hexserial
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nop
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TTYDBG("\r\n")
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nop
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|
|
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dadd t0, t0, 0x4
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bnez t1, 1b
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sub t1, t1, 1
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TTYDBG("END HT bus scan\r\n")
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nop
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#endif
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|
|
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#if 0//RESET Southbridge
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dli t0, 0x90000efdfc000cf9
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|
//li t0, 0xb8000cf9
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|
lb a0, 0x0(t0)
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li a0, 0x4
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sb a0, 0x0(t0)
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|
TTYDBG("RESETing HyperTransport\r\n")
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nop
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|
#endif
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|
#ifdef HT_RECONNECT
|
|
#ifdef HT_16bit //Write Southbridge to 16 bit width
|
|
TTYDBG("Setting HyperTransport Southbridge to be 16-bit width\r\n")
|
|
//li t0, 0xba000000
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|
dli t0, 0x90000efdfe000000
|
|
#li t1, 0x01 //DRIVER 16bit
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|
li t1, 0x11
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|
sb t1, 0x4b(t0)
|
|
lw a0, 0x48(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
#else
|
|
TTYDBG("Setting HyperTransport Southbridge to be 8-bit width\r\n")
|
|
//li t0, 0xba000000
|
|
dli t0, 0x90000efdfe000000
|
|
li t1, 0x00
|
|
sb t1, 0x4b(t0)
|
|
lw a0, 0x48(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
|
|
#endif
|
|
|
|
#ifdef HT_800M //Write Southbridge to 800Mhz
|
|
TTYDBG("Setting HyperTransport Southbridge to be 800M\r\n")
|
|
//li t0, 0xba000000
|
|
dli t0, 0x90000efdfe000000
|
|
#li t1, 0x2 //Frequency : 400Mhz
|
|
li t1, 0x5 //Frequency : 800Mhz
|
|
sb t1, 0x51(t0)
|
|
lw a0, 0x4c(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
#endif
|
|
|
|
#if 1 //Watch dog Trying
|
|
TTYDBG("Setting Watch Dog to make a WARM RESET\r\n")
|
|
#ifdef WD_DEBUG
|
|
TTYDBG("Setting Watch dog BAR\r\n")
|
|
nop
|
|
//li t0, 0xba00096c
|
|
dli t0, 0x90000efdfe00096c
|
|
lw a0, 0(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
#endif
|
|
//li t0, 0xba00096c
|
|
dli t0, 0x90000efdfe00096c
|
|
li a0, 0x00001000
|
|
sw a0, 0(t0)
|
|
nop
|
|
#ifdef WD_DEBUG
|
|
lw a0, 0(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
|
|
li t0, 0xb0001000
|
|
lw a0, 0x0(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
|
|
TTYDBG("Watch dog Disable\r\n")
|
|
//li t0, 0xba0009e8
|
|
dli t0, 0x90000efdfe0009e8
|
|
lw a0, 0(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
lw a0, 0(t0)
|
|
li a1, 0x04000000
|
|
or a0, a0, a1
|
|
|
|
sw a0, 0(t0)
|
|
nop
|
|
lw a0, 0(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
li t0, 0xb0001000
|
|
lw a0, 0x0(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
|
|
TTYDBG("Watch dog Enable\r\n")
|
|
//li t0, 0xba0009e8
|
|
dli t0, 0x90000efdfe0009e8
|
|
lw a0, 0(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
#endif
|
|
//li t0, 0xba0009e8
|
|
dli t0, 0x90000efdfe0009e8
|
|
lw a0, 0(t0)
|
|
li a1, 0xfbffffff
|
|
and a0, a0, a1
|
|
|
|
sw a0, 0(t0)
|
|
nop
|
|
#ifdef WD_DEBUG
|
|
lw a0, 0(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
li t0, 0xb0001000
|
|
lw a0, 0x0(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
|
|
TTYDBG("Watch dog counter value\r\n")
|
|
li t0, 0xb0001000
|
|
lw a0, 0x8(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
#endif
|
|
li t0, 0xb0001000
|
|
li a0, 0x1
|
|
sw a0, 0x8(t0)
|
|
|
|
TTYDBG("Watch dog begin to work\r\n")
|
|
li t0, 0xb0001000
|
|
li t1, 0x1
|
|
sw t1, 0(t0)
|
|
li t1, 0x81
|
|
sw t1, 0(t0)
|
|
li t0, 0xb0001000
|
|
lw a0, 0x0(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
|
|
TTYDBG("Watch dog counter value\r\n")
|
|
li t0, 0xb0001000
|
|
li t1, 0x1
|
|
1:
|
|
lw a0, 0x8(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
lw a0, 0x8(t0)
|
|
bne a0, t1, 1b
|
|
nop
|
|
|
|
#endif
|
|
|
|
#if 1//wait until HT link down
|
|
TTYDBG("Waiting HyperTransport bus to be down.")
|
|
dli t0, 0x90000efdfb000000
|
|
li t1, 0x1f
|
|
1:
|
|
lw a0, 0x44(t0)
|
|
#bal hexserial
|
|
nop
|
|
beqz t1,2f
|
|
TTYDBG(">")
|
|
addi t1, t1, -1
|
|
b 3f
|
|
nop
|
|
2:
|
|
TTYDBG("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b=")
|
|
li t1, 0x1f
|
|
|
|
3:
|
|
lw a0, 0x44(t0)
|
|
li a1, 0x20
|
|
and a0, a0, a1
|
|
|
|
bnez a0, 1b
|
|
nop
|
|
|
|
TTYDBG("\r\n")
|
|
lw a0, 0x44(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
#endif
|
|
|
|
#if 1//wait until HT link up
|
|
TTYDBG("Waiting HyperTransport bus to be up.")
|
|
dli t0, 0x90000efdfb000000
|
|
li t1, 0x1f
|
|
1:
|
|
lw a0, 0x44(t0)
|
|
#bal hexserial
|
|
nop
|
|
beqz t1,2f
|
|
TTYDBG(">")
|
|
addi t1, t1, -1
|
|
b 3f
|
|
nop
|
|
2:
|
|
TTYDBG("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b=")
|
|
li t1, 0x1f
|
|
|
|
3:
|
|
lw a0, 0x44(t0)
|
|
li a1, 0x20
|
|
and a0, a0, a1
|
|
|
|
beqz a0, 1b
|
|
nop
|
|
|
|
TTYDBG("\r\n")
|
|
lw a0, 0x44(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
#endif
|
|
|
|
#if 1
|
|
TTYDBG("Setting HyperTransport Southbridge back to be 8-bit width and 200Mhz for next RESET\r\n")
|
|
//li t0, 0xba000000
|
|
dli t0, 0x90000efdfe000000
|
|
li t1, 0x00
|
|
sb t1, 0x4b(t0)
|
|
lw a0, 0x48(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
//li t1, 0x0
|
|
//sb t1, 0x4d(t0)
|
|
//lw a0, 0x4c(t0)
|
|
//bal hexserial
|
|
//nop
|
|
//TTYDBG("\r\n")
|
|
#endif
|
|
#endif
|
|
|
|
|
|
#if 1//Check if CRC error bit set and reset it
|
|
#define RESET_CRC
|
|
crc_checking:
|
|
TTYDBG("Checking HyperTransport bus CRC error bit.\r\n")
|
|
dli t0, 0x90000efdfb000000
|
|
|
|
2:
|
|
lw a0, 0x44(t0)
|
|
li a1, 0x300
|
|
and a0, a0, a1
|
|
|
|
beqz a0, 1f
|
|
nop
|
|
|
|
lw a0, 0x44(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\nReset the Controller errror CRC bit\r\n")
|
|
nop
|
|
|
|
lw a0, 0x44(t0)
|
|
li a1, 0xfffffcff
|
|
and a0, a0, a1
|
|
|
|
sw a0, 0x44(t0)
|
|
nop
|
|
|
|
#ifdef RESET_CRC
|
|
b 2b
|
|
nop
|
|
#endif
|
|
|
|
1:
|
|
TTYDBG("Checking HyperTransport SouthBridge CRC error bit.\r\n")
|
|
//li t0, 0xba000000
|
|
dli t0, 0x90000efdfe000000
|
|
2:
|
|
lw a0, 0x48(t0)
|
|
li a1, 0x300
|
|
and a0, a0, a1
|
|
|
|
beqz a0, 1f
|
|
nop
|
|
|
|
lw a0, 0x48(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\nReset the Bridge errror CRC bit\r\n")
|
|
nop
|
|
|
|
lw a0, 0x48(t0)
|
|
li a1, 0xfffffcff
|
|
and a0, a0, a1
|
|
|
|
sw a0, 0x48(t0)
|
|
nop
|
|
|
|
#ifdef RESET_CRC
|
|
b 2b
|
|
nop
|
|
#endif
|
|
|
|
|
|
1:
|
|
TTYDBG("Done\r\n")
|
|
|
|
//b crc_checking
|
|
nop
|
|
#endif
|
|
|
|
#if 1//Read HT channel priority
|
|
TTYDBG("Read HT Channel priority\r\n")
|
|
dli t2, 0x90000efdfb000000
|
|
lw a0, 0x50(t2)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
#endif
|
|
|
|
|
|
#if 0//LPC header scan
|
|
li t1, 16
|
|
TTYDBG("start HT-LPC header scan\r\n")
|
|
|
|
//li t0, 0xba000800
|
|
dli t0, 0x90000efdfe000800
|
|
1:
|
|
move a0, t0
|
|
bal hexserial
|
|
nop
|
|
TTYDBG(" : ")
|
|
|
|
lw a0, 0x0(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
nop
|
|
|
|
dadd t0, t0, 0x4
|
|
|
|
bnez t1, 1b
|
|
sub t1, t1, 1
|
|
|
|
TTYDBG("END HT-LPC header scan\r\n")
|
|
nop
|
|
|
|
li t1, 6
|
|
//li t0, 0xba000810
|
|
dli t0, 0x90000efdfe000810
|
|
1:
|
|
li a0, 0xffffffff
|
|
|
|
sw a0, 0x0(t0)
|
|
nop
|
|
|
|
dadd t0, t0, 0x4
|
|
|
|
bnez t1, 1b
|
|
sub t1, t1, 1
|
|
|
|
|
|
li t1, 16
|
|
TTYDBG("start HT-LPC header scan\r\n")
|
|
|
|
//li t0, 0xba000800
|
|
dli t0, 0x90000efdfe000800
|
|
1:
|
|
move a0, t0
|
|
bal hexserial
|
|
nop
|
|
TTYDBG(" : ")
|
|
|
|
lw a0, 0x0(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
nop
|
|
|
|
dadd t0, t0, 0x4
|
|
|
|
bnez t1, 1b
|
|
sub t1, t1, 1
|
|
|
|
TTYDBG("END HT-LPC header scan\r\n")
|
|
nop
|
|
|
|
|
|
#endif
|
|
|
|
#if 1//Enable the LPC on the Southbridge, including SuperIO, LED....
|
|
TTYDBG("Check the LPC on the Southbridge\r\n")
|
|
//li t0, 0xba000800
|
|
dli t0, 0x90000efdfe000800
|
|
lw a0, 0x78(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
|
|
li a0, 0x19
|
|
sb a0, 0x7b(t0)
|
|
lw a0, 0x78(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
|
|
lw a0, 0xa4(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
|
|
li a1, 0x30000
|
|
sw a1, 0xa4(t0)
|
|
|
|
nop
|
|
nop
|
|
nop
|
|
|
|
lw a0, 0xa4(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
|
|
li a0,0xb8000080
|
|
li t0,0x0c
|
|
sb t0,0x0(a0)
|
|
sb t0,0x4(a0)
|
|
|
|
//li a0,0xb0000080
|
|
//li t0,0x0c
|
|
//sb t0,0x0(a0)
|
|
//sb t0,0x4(a0)
|
|
|
|
//li t0,0xb8000080
|
|
//li a0,0x0c
|
|
//sb a0,0x0(t0)
|
|
|
|
//lb a0, 0x00(t0)
|
|
//bal hexserial
|
|
//nop
|
|
//TTYDBG("\r\n")
|
|
|
|
//OUTPUT by COM1
|
|
//li t0, 0xba000800
|
|
dli t0, 0x90000efdfe000800
|
|
lw a0, 0xa0(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
|
|
li a0, 0xffffffff
|
|
sw a0, 0xa0(t0)
|
|
nop
|
|
lw a0, 0xa0(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
|
|
//UART A
|
|
li a0, 0x03ff03f8
|
|
sw a0, 0xa8(t0)
|
|
nop
|
|
lw a0, 0xa8(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
|
|
//PORT 80 for DEBUG LED
|
|
li a0, 0x00840080
|
|
sw a0, 0xac(t0)
|
|
nop
|
|
lw a0, 0xac(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
|
|
#if 1
|
|
//PORT 60 for KeyBoard
|
|
li a0, 0x007f0060
|
|
sw a0, 0xb0(t0)
|
|
nop
|
|
lw a0, 0xb0(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
#endif
|
|
|
|
//set Southbridge Super IO to be 24Mhz input
|
|
TTYDBG("Setting Southbridge Super IO to be 24Mhz input\r\n")
|
|
|
|
li a0, 0xffff0000
|
|
sw a0, 0xb4(t0)
|
|
nop
|
|
lw a0, 0xb4(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
|
|
//Start Super IO configuration KEYWORDS
|
|
li t0,0xb8000000
|
|
li a0, 0x87
|
|
sb a0, 0x2e(t0)
|
|
nop
|
|
sb a0, 0x2e(t0)
|
|
nop
|
|
li a0, 0x24
|
|
sb a0, 0x2e(t0)
|
|
nop
|
|
|
|
lb a0, 0x2f(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
|
|
lb a0, 0x2f(t0)
|
|
andi a0, a0, 0xbf
|
|
sb a0, 0x2f(t0)
|
|
nop
|
|
lb a0, 0x2f(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
|
|
li a0, 0xaa
|
|
sb a0, 0x2e(t0)
|
|
|
|
//Write Space 4 of LPC to NULL
|
|
//li t0, 0xba000800
|
|
dli t0, 0x90000efdfe000800
|
|
li a0, 0x0000
|
|
sw a0, 0xb4(t0)
|
|
nop
|
|
lw a0, 0xb4(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
#####endhere
|
|
|
|
bal initserial_COM1
|
|
nop
|
|
TTYDBG("Check out output of Southbridge UART port\r\n")
|
|
|
|
1:
|
|
TTYDBG_COM1("Loongson 3 PMON output from Southbridge\r\n")
|
|
nop
|
|
|
|
//li t0, 0xba000800
|
|
dli t0, 0x90000efdfe000800
|
|
lw a0, 0x78(t0)
|
|
bal hexserial_COM1
|
|
nop
|
|
TTYDBG_COM1("\r\n")
|
|
|
|
lw a0, 0xa4(t0)
|
|
bal hexserial_COM1
|
|
nop
|
|
TTYDBG_COM1("\r\n")
|
|
|
|
lw a0, 0xa0(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
|
|
li t0,0xb8000080
|
|
li a0,0x0E
|
|
sb a0,0x0(t0)
|
|
sb a0,0x4(t0)
|
|
|
|
#endif
|
|
|
|
#if 0 //DISABLE all other devices
|
|
TTYDBG("DISABLE all other HT device\r\n")
|
|
//li t0, 0xba000900
|
|
dli t0, 0x90000efdfe000900
|
|
lw a0, 0xe4(t0)
|
|
bal hexserial
|
|
nop
|
|
|
|
TTYDBG("\r\n")
|
|
nop
|
|
|
|
li t1, 0x7f7
|
|
or a0, a0, t1
|
|
sw a0, 0xe4(t0)
|
|
|
|
lw a0, 0xe4(t0)
|
|
bal hexserial
|
|
nop
|
|
|
|
TTYDBG("\r\n")
|
|
nop
|
|
|
|
lw a0, 0xe8(t0)
|
|
bal hexserial
|
|
nop
|
|
|
|
TTYDBG("\r\n")
|
|
nop
|
|
|
|
//li t1, 0x53fd27
|
|
li t1, 0x537d23//DMA,P2P enable
|
|
or a0, a0, t1
|
|
sw a0, 0xe8(t0)
|
|
|
|
lw a0, 0xe8(t0)
|
|
bal hexserial
|
|
nop
|
|
|
|
TTYDBG("\r\n")
|
|
nop
|
|
|
|
//li t0, 0xba000800
|
|
dli t0, 0x90000efdfe000800
|
|
lw a0, 0xa4(t0)
|
|
bal hexserial
|
|
nop
|
|
|
|
TTYDBG("\r\n")
|
|
nop
|
|
|
|
li t1, 0x10000
|
|
or a0, a0, t1
|
|
sw a0, 0xa4(t0)
|
|
|
|
lw a0, 0xa4(t0)
|
|
bal hexserial
|
|
nop
|
|
|
|
TTYDBG("\r\nD1,F0, 0x88\r\n")
|
|
nop
|
|
|
|
//li t0, 0xba000800
|
|
dli t0, 0x90000efdfe000800
|
|
lw a0, 0x88(t0)
|
|
bal hexserial
|
|
nop
|
|
|
|
TTYDBG("\r\nD1,F0, 0x78\r\n")
|
|
|
|
lw a0, 0x78(t0)
|
|
bal hexserial
|
|
nop
|
|
|
|
TTYDBG("\r\nD1,F1, 0x60\r\n")
|
|
|
|
//li t0, 0xba000900
|
|
dli t0, 0x90000efdfe000900
|
|
lw a0, 0x60(t0)
|
|
bal hexserial
|
|
nop
|
|
|
|
TTYDBG("\r\nD1,F1, 0x64\r\n")
|
|
|
|
lw a0, 0x64(t0)
|
|
bal hexserial
|
|
nop
|
|
|
|
#endif
|
|
|
|
#if 0//read HT-PCI bridge header
|
|
|
|
li t1, 16
|
|
TTYDBG("start HT-PCI header scan\r\n")
|
|
|
|
//li t0, 0xba004000
|
|
dli t0, 0x90000efdfe004000
|
|
1:
|
|
move a0, t0
|
|
bal hexserial
|
|
nop
|
|
TTYDBG(" : ")
|
|
|
|
lw a0, 0x0(t0)
|
|
bal hexserial
|
|
nop
|
|
TTYDBG("\r\n")
|
|
nop
|
|
|
|
dadd t0, t0, 0x4
|
|
|
|
bnez t1, 1b
|
|
sub t1, t1, 1
|
|
|
|
TTYDBG("END HT-PCI header scan\r\n")
|
|
nop
|
|
#endif
|
|
|
|
#endif
|
|
|