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70 lines
1.2 KiB
70 lines
1.2 KiB
/*whd : loongson3_fixup.S
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used to fix up the potential addressing miss
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caused by speculated execution
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*/
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sync
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/* open L2 Xbar interleave for Scache
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dli t1, 0x900000003ff00400
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lw a0, 0(t1)
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ori a0, 0x10
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sw a0, 0(t1)
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*/
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dli t2, 0x900000003ff02000
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dli t1, 0x900000003ff02800
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TTYDBG("Fix L1xbar illegal access at NODE 0\r\n")
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1:
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####### Unused HT0 port #########################
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dli t0, 0x00000c0000000000
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sd t0, 0x28(t2)
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dli t0, 0x00000c0000000000
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sd t0, 0x68(t2)
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dli t0, 0x00000c00000000f7
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sd t0, 0xa8(t2)
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dli t0, 0x0000200000000000
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sd t0, 0x30(t2)
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dli t0, 0x0000200000000000
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sd t0, 0x70(t2)
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dli t0, 0x00002000000000f7
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sd t0, 0xb0(t2)
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dli t0, 0x0000100000000000
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sd t0, 0x38(t2)
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dli t0, 0x0000300000000000
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sd t0, 0x78(t2)
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dli t0, 0x00001000000000f7
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sd t0, 0xb8(t2)
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daddiu t2, t2, 0x100
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bne t2, t1, 1b
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nop
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TTYDBG("Fix L2xbar in NODE 0\r\n")
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//order cann't be changed.
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dli t2, 0x900000003ff00000
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dli t0, 0xfffffffffff00000
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sd t0, 0x40(t2)
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dli t0, 0x000000001fc000f2
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sd t0, 0x80(t2)
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dli t0, 0x000000001fc00000
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sd t0, 0x0(t2)
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dli t0, 0x0000000010000000
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sd t0, 0x08(t2)
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dli t0, 0xfffffffff0000000
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sd t0, 0x48(t2)
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dli t0, 0x0000000010000082
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sd t0, 0x88(t2)
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sd zero, 0x90(t2)
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sync
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