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113 lines
3.8 KiB
113 lines
3.8 KiB
#include "sb700.h"
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#include "rs780_cmn.h"
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static void pci_init(device_t dev)
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{
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u32 dword;
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u16 word;
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u8 byte;
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/* RPR 5.1 Enables the PCI-bridge subtractive decode */
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/* This setting is strongly recommended since it supports some legacy PCI add-on cards,such as BIOS debug cards */
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printk_info("Enables the PCI-bridge subtractive decode\n");
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byte = pci_read_config8(dev, 0x4B);
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byte |= 1 << 7;
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pci_write_config8(dev, 0x4B, byte);
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byte = pci_read_config8(dev, 0x40);
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byte |= 1 << 5;
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pci_write_config8(dev, 0x40, byte);
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//vga pci card support //lycheng
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/* PCI Command: Enable IO response */
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byte = pci_read_config8(dev, 0x04);
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byte |= (1 << 0)|(1 << 5)|(1 << 1)|(1 << 2);
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pci_write_config8(dev, 0x04, byte);
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/* PCI Command: VGA enable */
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byte = pci_read_config8(dev, 0x3e);
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byte |= (1 << 3);
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pci_write_config8(dev, 0x3e, byte);
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//end vga pci card support
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/* RPR5.2 PCI-bridge upstream dual address window */
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/* this setting is applicable if the system memory is more than 4GB,and the PCI device can support dual address access */
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printk_info("PCI-bridge upstream dual address window\n");
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byte = pci_read_config8(dev, 0x50);
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//byte |= 1 << 0;
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byte &= ~(1 << 0);
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pci_write_config8(dev, 0x50, byte);
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/* RPR 5.3 PCI bus 64-byte DMA read access */
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/* Enhance the PCI bus DMA performance */
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printk_info("PCI bus 64-byte DMA read access\n");
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byte = pci_read_config8(dev, 0x4B);
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byte |= 1 << 4;
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pci_write_config8(dev, 0x4B, byte);
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/* RPR 5.4 Enables the PCIB writes to be cacheline aligned. */
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/* The size of the writes will be set in the Cacheline Register */
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printk_info("Enables the PCIB writes to be cacheline aligned.\n");
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byte = pci_read_config8(dev, 0x40);
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byte |= 1 << 1;
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pci_write_config8(dev, 0x40, byte);
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/* RPR 5.5 Enables the PCIB to retain ownership of the bus on the Primary side and on the Secondary side when GNT# is deasserted */
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printk_info("Enables the PCIB to retain ownership of the bus\n");
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pci_write_config8(dev, 0x0D, 0x40);
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pci_write_config8(dev, 0x1B, 0x40);
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/* RPR 5.6 Enable the command matching checking function on "Memory Read" & "Memory Read Line" commands */
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printk_info("Enable the command matching checking function\n");
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byte = pci_read_config8(dev, 0x4B);
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byte |= 1 << 6;
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pci_write_config8(dev, 0x4B, byte);
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/* RPR 5.7 When enabled, the PCI arbiter checks for the Bus Idle before asserting GNT# */
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printk_info("the PCI arbiter checks for the Bus Idle before asserting GNT#\n");
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byte = pci_read_config8(dev, 0x4B);
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byte |= 1 << 0;
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pci_write_config8(dev, 0x4B, byte);
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/* RPR 5.8 Adjusts the GNT# de-assertion time */
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printk_info("Adjusts the GNT# de-assertion time\n");
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word = pci_read_config16(dev, 0x64);
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word |= 1 << 12;
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pci_write_config16(dev, 0x64, word);
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/* RPR 5.9 Fast Back to Back transactions support */
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printk_info("Fast Back to Back transactions support\n");
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byte = pci_read_config8(dev, 0x48);
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byte |= 1 << 2;
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/* pci_write_config8(dev, 0x48, byte); */
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/* RPR 5.10 Enable Lock Operation */
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/* byte = pci_read_config8(dev, 0x48); */
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byte |= 1 << 3;
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pci_write_config8(dev, 0x48, byte);
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/* RPR 5.11 Enable additional optional PCI clock */
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printk_info("Enable additional optional PCI clock\n");
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word = pci_read_config16(dev, 0x64);
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word |= 1 << 8;
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pci_write_config16(dev, 0x64, word);
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/* RPR 5.12 Enable One-Prefetch-Channel Mode */
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printk_info("Enable One-Prefetch-Channel Mode\n");
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dword = pci_read_config32(dev, 0x64);
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dword |= 1 << 20;
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pci_write_config32(dev, 0x64, dword);
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/* RPR 5.13 Disable PCIB MSI Capability */
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printk_info("Disable PCIB MSI Capability\n");
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byte = pci_read_config8(dev, 0x40);
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byte &= ~(1 << 3);
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pci_write_config8(dev, 0x40, byte);
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/* rpr5.14 Adjusting CLKRUN# */
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printk_info("Adjusting CLKRUN\n");
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dword = pci_read_config32(dev, 0x64);
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dword |= (1 << 15);
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pci_write_config32(dev, 0x64, dword);
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}
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