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285 lines
5.2 KiB
285 lines
5.2 KiB
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/*whd : loongson3_fixup.S
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used to fix up the potential addressing miss
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caused by speculated execution
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*/
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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sync
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sync
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sync
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sync
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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#if 0
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#set XBAR to route all the DMA request to Scache0
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/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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THIS CONFIGURATION WILL AFFECT the Scache initilization,
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The Scache init MUST BE rewrite when reconfiguared
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!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */
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#define SINGLE_SCACHE
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#ifdef SINGLE_SCACHE
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dli a0,0xf #using 37:36
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#else
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dli a0,0x2 #using 11:10
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#endif
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dli t0,0x900000003ff00400
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sd a0,0x0(t0)
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dli t0,0x900010003ff04400
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sd a0,0x0(t0)
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#if 1//config L1 xbar cpu port
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TTYDBG("Using Scache 0 \r\n")
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dli t2, 0x900000003ff02000
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dli t1, 0x900000003ff02800
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1:
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dli t0, 0x0000000000000000
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sd t0, 0x38(t2)
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dli t0, 0xfffff00000000000
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sd t0, 0x78(t2)
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dli t0, 0x00000000000000f2
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sd t0, 0xb8(t2)
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daddi t2,0x100
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bne t2,t1,1b;
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nop
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PRINTSTR("Scache index setup done\r\n")
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#endif
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#endif
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#ifdef MULTI_CHIP
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#if 0
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TTYDBG("HT0 frequency reconfig @CPU1 NODE3\r\n")
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###################### HT@CPU1
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dli a0, 0x90002efdfb000000
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//set 800 Mhz HT HOST
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lw a1, 0x48(a0)
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li a2, 0x500 ##800Mhz
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or a1, a1, a2
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sw a1, 0x48(a0)
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//set 8 bit HT HOST
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lw a1, 0x44(a0)
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li a2, 0x88ffffff ##8bit mode
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and a1, a1, a2 ##set to 8 bit mode
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li a2, 0x11000000 ##16bit
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or a1, a1, a2
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sw a1, 0x44(a0)
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###################### HT@CPU0
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dli a0, 0x90000efdfb000000
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//set 800 Mhz HT HOST
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lw a1, 0x48(a0)
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li a2, 0x500 ##800Mhz
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or a1, a1, a2 ##
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sw a1, 0x48(a0)
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//set 8 bit HT HOST
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lw a1, 0x44(a0)
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li a2, 0x88ffffff ##8bit mode
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and a1, a1, a2 ##set to 8 bit mode
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li a2, 0x11000000 ##16bit
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or a1, a1, a2
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sw a1, 0x44(a0)
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###################### Disconnect
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dli a0, 0x90000efdfb000000
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//Disconnect HT BUS
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lw a1, 0x50(a0)
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li a2, 0x40000000
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or a1, a1, a2
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sw a1, 0x50(a0)
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##################################################
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#endif
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#endif
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#if 1
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//config L1 xbar cpu port
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TTYDBG("Fix L1xbar illegal access from core0 to core3\r\n")
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dli t2, 0x900000003ff02000
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dli t1, 0x900000003ff02800
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1:
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####### Unused HT0 port #########################
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dli t0, 0x00000c0000000000
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sd t0, 0x30(t2)
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dli t0, 0x00000c0000000000
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sd t0, 0x70(t2)
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dli t0, 0x00000c00000000f4
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sd t0, 0xb0(t2)
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daddiu t2, t2, 0x100
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bne t2, t1, 1b
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nop
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#ifdef MULTI_CHIP
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TTYDBG("Fix L1xbar illegal access from core4 to core7\r\n")
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dli t2, 0x900010003ff06000
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dli t1, 0x900010003ff06500
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1:
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####### Unused HT0 port #########################
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dli t0, 0x00000c0000000000
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sd t0, 0x28(t2)
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dli t0, 0x00000c0000000000
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sd t0, 0x68(t2)
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dli t0, 0x00000c00000000f7
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sd t0, 0xa8(t2)
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daddiu t2, t2, 0x100
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bne t2, t1, 1b
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nop
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#endif
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#endif
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#if 1 //LC modify
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#ifdef DUAL_3B
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TTYDBG("Fix L1xbar illegal access from core8 to core11\r\n")
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dli t2, 0x900020003ff0a000
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dli t1, 0x900020003ff0a500
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1:
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####### Unused HT0 port #########################
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dli t0, 0x00002c0000000000
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sd t0, 0x28(t2)
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dli t0, 0x00003c0000000000
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sd t0, 0x68(t2)
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dli t0, 0x00003c00000000f4
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sd t0, 0xa8(t2)
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daddiu t2, t2, 0x100
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bne t2, t1, 1b
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nop
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TTYDBG("Fix L1xbar illegal access from core12 to core15\r\n")
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dli t2, 0x900030003ff0e000
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dli t1, 0x900030003ff0e500
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1:
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####### Unused HT0 port #########################
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dli t0, 0x00002c0000000000
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sd t0, 0x28(t2)
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dli t0, 0x00002c0000000000
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sd t0, 0x68(t2)
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dli t0, 0x00002c00000000f7
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sd t0, 0xa8(t2)
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daddiu t2, t2, 0x100
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bne t2, t1, 1b
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nop
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#endif
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#endif
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#if 1
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############
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TTYDBG("Fix L2xbar in NODE 0\r\n")
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dli t2, 0x900000003ff00000
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dli t0, 0xfffffffffff00000
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sd t0, 0x40(t2)
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dli t0, 0x000000001fc000f2
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sd t0, 0x80(t2)
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dli t0, 0x000000001fc00000
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sd t0, 0x0(t2)
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############ 0x10000000 Set to not allow Cache access #######
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dli t0, 0x0000000010000082
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sd t0, 0x88(t2)
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sd $0, 0x90(t2)
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#endif
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#ifdef MULTI_CHIP
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TTYDBG("Fix L2xbar in NODE 1\r\n")
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dli t2, 0x900010003ff04000
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dli t0, 0x0000100010000000
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sd t0, 0x08(t2)
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dli t0, 0xfffffffff0000000
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sd t0, 0x48(t2)
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dli t0, 0x0000000010000082
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sd t0, 0x88(t2)
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sd $0, 0x80(t2)
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sd $0, 0x90(t2)
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#ifdef DUAL_3B
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TTYDBG("Fix L2xbar in NODE 2\r\n")
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dli t2, 0x900020003ff08000
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dli t0, 0x0000200010000000
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sd t0, 0x08(t2)
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dli t0, 0xfffffffff0000000
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sd t0, 0x48(t2)
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dli t0, 0x0000000010000082
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sd t0, 0x88(t2)
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sd $0, 0x80(t2)
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sd $0, 0x90(t2)
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TTYDBG("Fix L2xbar in NODE 3\r\n")
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dli t2, 0x900030003ff0c000
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dli t0, 0x0000300010000000
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sd t0, 0x08(t2)
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dli t0, 0xfffffffff0000000
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sd t0, 0x48(t2)
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dli t0, 0x0000000010000082
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sd t0, 0x88(t2)
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sd $0, 0x80(t2)
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sd $0, 0x90(t2)
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#endif
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#endif
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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sync
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sync
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sync
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sync
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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