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768 lines
16 KiB
768 lines
16 KiB
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//extern onintr(int a,int *b);
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//#include "mips/cpu.h"
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#include "mips/prid.h"
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#include "mips.h"
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#include "pmon.h"
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#ifdef R3081
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#include "r3081.h"
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#endif
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#ifdef R3041
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#include "r3041.h"
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#endif
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#include "ri.h"
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static unsigned long
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mips_get_word_l(struct pt_regs *xcp, void *va, int *perr)
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{
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*perr = 0;
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return(*(unsigned long *)va);
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}
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static int
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mips_put_word_l(struct pt_regs *xcp, void *va, unsigned long val)
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{
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*(unsigned long *)va = val;
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return 0;
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}
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static int emu_lwl(struct pt_regs * regs,mips_instruction ir,vaddr_t_l emulpc)
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{ int err = 0;
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/*the "ir" is the instruction causing the exception*/
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/*get the real address,perhaps the address is not word aligned*/
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void *va = REG_TO_VA_l (regs->regs[MIPSInst_RS(ir)])+ MIPSInst_SIMM(ir);
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unsigned long addr = 0;
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unsigned long emul_pc = (unsigned long)emulpc;
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unsigned long little_three_bits;
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unsigned long value,value_tmp;
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// printf("emu_lwl\r\n");
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/*compute the correct position in the RT*/
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/*note !!!!: we have supposed the CPU is little_Endianness and status regiester's RE bit =0 */
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/*little Endianness*/
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little_three_bits = (unsigned long)va&(0x7);
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value_tmp = regs->regs[MIPSInst_RT(ir)];
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switch(little_three_bits) {
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case 0:
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case 4:
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/*must check lwl valid*/
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addr = (unsigned long) va;
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check_axs(emul_pc,addr,4);
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value = mips_get_word_l(regs,va,&err);
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if(err){
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return SIGBUS;
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}
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value<<=24;
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value_tmp &= 0xffffff;
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regs->regs[MIPSInst_RT(ir)] =value_tmp|value;
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break;
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case 1:
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case 5:
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addr = (unsigned long)va -1;
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check_axs(emul_pc,addr,4);
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value = mips_get_word_l(regs,(void *)((unsigned long) va-1),&err);
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if(err){
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return SIGBUS;
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}
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value<<=16;
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value_tmp&=0xffff;
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regs->regs[MIPSInst_RT(ir)] =value_tmp|value;
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break;
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case 2:
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case 6:
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addr = (unsigned long)va - 2;
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check_axs(emul_pc,addr,4);
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value = mips_get_word_l(regs,(void *)((unsigned long)va-2),&err);
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if(err){
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return SIGBUS;
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}
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value<<=8;
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value_tmp &= 0xff;
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regs->regs[MIPSInst_RT(ir)] =value_tmp|value;
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break;
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case 3:
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case 7:
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addr = (unsigned long)va - 3;
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check_axs(emul_pc,addr,4);
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value = mips_get_word_l(regs,(void *)((unsigned long)va-3),&err);
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if(err){
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return SIGBUS;
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};
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regs->regs[MIPSInst_RT(ir)] = value;
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break;
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} /*swith ended*/
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return 0;
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}
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static int emu_lwr(struct pt_regs *regs,mips_instruction ir,vaddr_t_l emulpc)
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{ int err = 0;
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/*the "ir" is the instruction causing the exception*/
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/*get the real address,perhaps the address is not word aligned*/
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void *va = REG_TO_VA_l (regs->regs[MIPSInst_RS(ir)])
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+ MIPSInst_SIMM(ir);
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unsigned long addr;
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unsigned long emul_pc = (unsigned long)emulpc;
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unsigned long little_three_bits;
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unsigned long value,value_tmp;
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// printf("emu_lwr\r\n");
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/*compute the correct position in the RT*/
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/*note !!!!: we have supposed the CPU is little_Endianness and status regiester's RE bit =0 */
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little_three_bits = (unsigned long)va&(0x7);
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value_tmp = regs->regs[MIPSInst_RT(ir)];
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switch(little_three_bits) {
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case 0:
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case 4:
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/*must check lwl valid*/
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addr = (unsigned long)va ;
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check_axs(emul_pc,addr,4);
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value = mips_get_word_l(regs,va,&err);
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if(err){
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return SIGBUS;
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}
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regs->regs[MIPSInst_RT(ir)] =value;
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break;
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case 1:
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case 5:
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addr = (unsigned long)va -1;
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check_axs(emul_pc,addr,4);
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value = mips_get_word_l(regs,(void *)((unsigned long)va-1),&err);
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if(err){
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return SIGBUS;
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}
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value>>=8;
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value_tmp&=0xff000000;
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regs->regs[MIPSInst_RT(ir)] =value_tmp|value;
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break;
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case 2:
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case 6:
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addr = (unsigned long)va-2;
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check_axs(emul_pc,addr,4);
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value = mips_get_word_l(regs,(void *)((unsigned long)va-2),&err);
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if(err){
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return SIGBUS;
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}
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value>>=16;
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value_tmp &= 0xffff0000;
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regs->regs[MIPSInst_RT(ir)] =value_tmp|value;
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break;
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case 3:
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case 7:
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addr = (unsigned long)va -3;
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check_axs(emul_pc,addr,4);
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value = mips_get_word_l(regs,(void *)((unsigned long)va-3),&err);
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if(err){
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return SIGBUS;
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};
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value>>=24;
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value_tmp &= 0xffffff00;
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regs->regs[MIPSInst_RT(ir)] = value_tmp|value;
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break;
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} /*swith ended*/
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return 0;
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}
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static int emu_swl(struct pt_regs *regs,mips_instruction ir, vaddr_t_l emulpc)
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{
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int err = 0;
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/*the "ir" is the instruction causing the exception*/
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/*get the real address,perhaps the address is not word aligned*/
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void *va = REG_TO_VA_l (regs->regs[MIPSInst_RS(ir)])
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+ MIPSInst_SIMM(ir);
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unsigned long addr;
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unsigned long emul_pc = (unsigned long)emulpc;
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unsigned long little_three_bits;
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unsigned long value,value_tmp;
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// printf("emu_swl\r\n");
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/*compute the correct position in the RT*/
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/*note !!!!: we have supposed the CPU is little_Endianness and status re
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* giester's RE bit =0 */
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little_three_bits = (unsigned long)va&(0x7);
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value_tmp = regs->regs[MIPSInst_RT(ir)];
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switch(little_three_bits) {
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case 0:
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case 4:
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addr = (unsigned long)va;
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check_axs(emul_pc,addr,4);
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value_tmp >>= 24;
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value = mips_get_word_l(regs,va,&err);
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if(err){
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return SIGBUS;
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}
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value &=0xffffff00;
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value |= value_tmp;
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if(mips_put_word_l(regs,va,value)){
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return SIGBUS;
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}
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break;
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case 1:
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case 5:
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addr = (unsigned long)va -1;
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check_axs(emul_pc,addr,4);
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value_tmp >>= 16;
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value = mips_get_word_l(regs,(void *)((unsigned long)va-1),&err);
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if(err){
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return SIGBUS;
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}
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value &=0xffff0000;
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value |= value_tmp;
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if(mips_put_word_l(regs,(void *)((unsigned long)va-1),value)){
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return SIGBUS;
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}
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break;
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case 2:
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case 6:
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addr = (unsigned long)va - 2;
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check_axs(emul_pc,addr,4);
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value_tmp >>= 8;
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value = mips_get_word_l(regs,(void *)((unsigned long)va-2),&err);
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if(err){
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return SIGBUS;
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}
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value &=0xff000000;
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value |= value_tmp;
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if(mips_put_word_l(regs,(void *)((unsigned long)va-2),value)){
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return SIGBUS;
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}
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break;
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case 3:
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case 7:
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addr = (unsigned long)va - 3;
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check_axs(emul_pc,addr,4);
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value = value_tmp;
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if(mips_put_word_l(regs,(void *)((unsigned long)va-3),value)){
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return SIGBUS;
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}
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break;
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}
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return 0;
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}
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static int emu_swr(struct pt_regs *regs,mips_instruction ir, vaddr_t_l emulpc)
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{
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int err = 0;
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/*the "ir" is the instruction causing the exception*/
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/*get the real address,perhaps the address is not word aligned*/
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void *va = REG_TO_VA_l (regs->regs[MIPSInst_RS(ir)])
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+ MIPSInst_SIMM(ir);
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unsigned long addr;
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unsigned long emul_pc = (unsigned long)emulpc;
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unsigned long little_three_bits;
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unsigned long value,value_tmp;
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// printf("emu_swr\r\n");
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/*compute the correct position in the RT*/
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/*note !!!!: we have supposed the CPU is little_Endianness and status re
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* giester's RE bit =0 */
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little_three_bits = (unsigned long)va&(0x7);
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value_tmp = regs->regs[MIPSInst_RT(ir)];
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switch(little_three_bits) {
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case 0:
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case 4:
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addr = (unsigned long) va;
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check_axs(emul_pc,addr,4);
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value = value_tmp;
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if(mips_put_word_l(regs,va,value)){
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return SIGBUS;
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}
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break;
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case 1:
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case 5:
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addr = (unsigned long)va -1;
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check_axs(emul_pc,addr,4);
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value_tmp <<= 8;
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value = mips_get_word_l(regs,(void *)((unsigned long)va-1),&err);
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if(err){
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return SIGBUS;
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}
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value &=0xff;
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value |= value_tmp;
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if(mips_put_word_l(regs,(void *)((unsigned long)va-1),value)){
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return SIGBUS;
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}
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break;
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case 2:
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case 6:
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addr = (unsigned long)va - 2;
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check_axs(emul_pc,addr,4);
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value_tmp <<= 16;
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value = mips_get_word_l(regs,(void *)((unsigned long)va-2),&err);
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if(err){
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return SIGBUS;
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}
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value &=0xffff;
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value |= value_tmp;
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if(mips_put_word_l(regs,(void *)((unsigned long)va-2),value)){
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return SIGBUS;
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}
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break;
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case 3:
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case 7:
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addr = (unsigned long)va -3;
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check_axs(emul_pc,addr,4);
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value_tmp <<= 24;
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value = mips_get_word_l(regs,(void *)((unsigned long)va-3),&err);
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if(err){
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return SIGBUS;
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}
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value &= 0xffffff;
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value |= value_tmp;
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if(mips_put_word_l(regs,(void *)((unsigned long)va-3),value)){
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return SIGBUS;
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}
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break;
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}
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return 0;
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}
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static int emu_div(struct pt_regs *regs,mips_instruction ir)
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{
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int x,y;
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int flag = 0;
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int quotient = 0,remainder = 0;
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unsigned int absx,absy,absquotient = 0,absremainder = 0,bm = 1;
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/*the "ir" is the instruction causing the exception*/
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x = regs->regs[MIPSInst_RS(ir)];
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y = regs->regs[MIPSInst_RT(ir)];
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#ifdef __test_ri__
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//printf("now in function:emu_div().\r\n");
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#endif
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if( y == 0 ) {/*overflow*/
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return SIGABRT;
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}
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/*x and y ?????Ƿ???ͬ*/
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flag = (x&0x80000000)^(y&0x80000000);
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/*get the abs(x)*/
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if(x<0){
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absx = (unsigned int)-x;
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}else {
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absx = (unsigned int)x;
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}
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/*get the abs(y)*/
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if(y<0){
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absy = (unsigned int) -y;
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}else {
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absy = (unsigned int)y;
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}
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/*caculate the absx/absy*/
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if(absx<absy) {/*don't need to calculate*/
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absquotient = 0;
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absremainder = absx;
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goto end;
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}
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while(!(absy&0x80000000))
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{ absy<<=1;
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if(absx<absy){
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absy>>= 1;
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break;
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}
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bm<<=1;
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}
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for(;bm;bm>>=1){
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if(absx>=absy){
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absx -= absy;
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absquotient |= bm;
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if(absx == 0)
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break;
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}
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absy >>= 1;
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}
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absremainder = absx;
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end:
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if( flag ){/*????????*/
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quotient = -absquotient;
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remainder = x-quotient*y;
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}else {
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quotient = absquotient;
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remainder = x - quotient*y;
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}
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regs->lo =(unsigned long)quotient;
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regs->hi = (unsigned long)remainder;
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#ifdef __test_ri__
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// printf("x is: %d\r\n",x);
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// printf("y is: %d\r\n",y);
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// printf("result is: %d (:\r\n",quotient);
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#endif
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return 0;
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}
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static int emu_divu(struct pt_regs *regs,mips_instruction ir)
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{
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unsigned int x,y,bm=1;
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unsigned int quotient = 0,remainder = 0;
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/*the "ir" is the instruction causing the exception*/
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x = regs->regs[MIPSInst_RS(ir)];
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y = regs->regs[MIPSInst_RT(ir)];
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if( y == 0 ) {/*overflow*/
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return SIGABRT;
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}
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if(x<y) {/*don't need to calculate*/
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quotient = 0;
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remainder = x;
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goto end;
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}
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while(!(y&0x80000000))
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{ y<<=1;
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if(x<y){
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y>>= 1;
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break;
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}
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bm<<=1;
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}
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for(;bm;bm>>=1){
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if(x>=y){
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x -= y;
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quotient |= bm;
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if(x == 0)
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break;
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}
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y >>= 1;
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}
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remainder = x;
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end:
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regs->lo = quotient;
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regs->hi = remainder;
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return 0;
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}
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/*
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* Compute the return address and do emulate branch simulation, if required.
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*/
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#define EFAULT 1
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int __compute_return_epc(struct pt_regs *regs)
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{
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unsigned int *addr, bit, fcr31;
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long epc;
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mips_instruction insn;
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epc = regs->cp0_epc;
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if (epc & 3) {
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printf("%s: unaligned epc - sending SIGBUS.\n");
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// force_sig(SIGBUS, current);
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return -EFAULT;
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}
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/*
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* Read the instruction
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*/
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addr = (unsigned int *) (unsigned long) epc;
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#if 0
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if (__get_user(insn, addr)) {
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printf("%s: bad epc value - sending SIGSEGV.\n");
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// force_sig(SIGSEGV, current);
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return -EFAULT;
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}
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#endif
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//bjzheng add __get_user is prevent page_fault exception,if this occurs,load from disk,but now my whole code is in ram.
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insn=*addr;
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// printf("instruction is %x",insn);
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regs->regs[0] = 0;
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switch (MIPSInst_OPCODE(insn)) {
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/*
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* jr and jalr are in r_format format.
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*/
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case spec_op:
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switch (MIPSInst_FUNC(insn)) {
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case jalr_op:
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regs->regs[MIPSInst_RD(insn)] = epc + 8;
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/* Fall through */
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case jr_op:
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regs->cp0_epc = regs->regs[MIPSInst_RS(insn)];
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break;
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}
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break;
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/*
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* This group contains:
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* bltz_op, bgez_op, bltzl_op, bgezl_op,
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* bltzal_op, bgezal_op, bltzall_op, bgezall_op.
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*/
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case bcond_op:
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switch (MIPSInst_RT(insn)) {
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case bltz_op:
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case bltzl_op:
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if ((long)regs->regs[MIPSInst_RS(insn)] < 0)
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epc = epc + 4 + (MIPSInst_SIMM(insn) << 2);
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else
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epc += 8;
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regs->cp0_epc = epc;
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break;
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case bgez_op:
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case bgezl_op:
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if ((long)regs->regs[MIPSInst_RS(insn)] >= 0)
|
|
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2);
|
|
else
|
|
epc += 8;
|
|
regs->cp0_epc = epc;
|
|
break;
|
|
|
|
case bltzal_op:
|
|
case bltzall_op:
|
|
regs->regs[31] = epc + 8;
|
|
if ((long)regs->regs[MIPSInst_RS(insn)] < 0)
|
|
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2);
|
|
else
|
|
epc += 8;
|
|
regs->cp0_epc = epc;
|
|
break;
|
|
|
|
case bgezal_op:
|
|
case bgezall_op:
|
|
regs->regs[31] = epc + 8;
|
|
if ((long)regs->regs[MIPSInst_RS(insn)] >= 0)
|
|
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2);
|
|
else
|
|
epc += 8;
|
|
regs->cp0_epc = epc;
|
|
break;
|
|
}
|
|
break;
|
|
|
|
/*
|
|
* These are unconditional and in j_format.
|
|
*/
|
|
case jal_op:
|
|
regs->regs[31] = regs->cp0_epc + 8;
|
|
case j_op:
|
|
epc += 4;
|
|
epc >>= 28;
|
|
epc <<= 28;
|
|
epc |= (MIPSInst_JTARGET(insn) << 2);
|
|
regs->cp0_epc = epc;
|
|
break;
|
|
|
|
/*
|
|
* These are conditional and in i_format.
|
|
*/
|
|
case beq_op:
|
|
case beql_op:
|
|
if (regs->regs[MIPSInst_RS(insn)] ==
|
|
regs->regs[MIPSInst_RT(insn)])
|
|
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2);
|
|
else
|
|
epc += 8;
|
|
regs->cp0_epc = epc;
|
|
break;
|
|
|
|
case bne_op:
|
|
case bnel_op:
|
|
if (regs->regs[MIPSInst_RS(insn)] !=
|
|
regs->regs[MIPSInst_RT(insn)])
|
|
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2);
|
|
else
|
|
epc += 8;
|
|
regs->cp0_epc = epc;
|
|
break;
|
|
|
|
case blez_op: /* not really i_format */
|
|
case blezl_op:
|
|
/* rt field assumed to be zero */
|
|
if ((long)regs->regs[MIPSInst_RS(insn)] <= 0)
|
|
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2);
|
|
else
|
|
epc += 8;
|
|
regs->cp0_epc = epc;
|
|
break;
|
|
|
|
case bgtz_op:
|
|
case bgtzl_op:
|
|
/* rt field assumed to be zero */
|
|
if ((long)regs->regs[MIPSInst_RS(insn)] > 0)
|
|
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2);
|
|
else
|
|
epc += 8;
|
|
regs->cp0_epc = epc;
|
|
break;
|
|
|
|
/*
|
|
* And now the FPA/cp1 branch instructions.
|
|
*/
|
|
case cop1_op:
|
|
#ifdef CONFIG_MIPS_FPU_EMULATOR
|
|
if(!(mips_cpu.options & MIPS_CPU_FPU))
|
|
fcr31 = current->tss.fpu.soft.sr;
|
|
else
|
|
#endif
|
|
asm ("cfc1\t%0,$31":"=r" (fcr31));
|
|
bit = (MIPSInst_RT(insn) >> 2);
|
|
bit += (bit != 0);
|
|
bit += 23;
|
|
switch (MIPSInst_RT(insn)) {
|
|
case 0: /* bc1f */
|
|
case 2: /* bc1fl */
|
|
if (~fcr31 & (1 << bit))
|
|
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2);
|
|
else
|
|
epc += 8;
|
|
regs->cp0_epc = epc;
|
|
break;
|
|
|
|
case 1: /* bc1t */
|
|
case 3: /* bc1tl */
|
|
if (fcr31 & (1 << bit))
|
|
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2);
|
|
else
|
|
epc += 8;
|
|
regs->cp0_epc = epc;
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int do_ri (struct pt_regs *xcp)
|
|
{
|
|
mips_instruction ir;
|
|
vaddr_t_l emulpc;
|
|
vaddr_t_l contpc;
|
|
int err = 0;
|
|
int sig;
|
|
|
|
|
|
ir = mips_get_word_l(xcp, REG_TO_VA_l xcp->cp0_epc, &err);
|
|
if (err) {
|
|
return SIGBUS;
|
|
}
|
|
|
|
/* XXX NEC Vr54xx bug workaround */
|
|
/* if ((xcp->cp0_cause & CAUSEF_BD) && !isBranchInstr (&ir))
|
|
xcp->cp0_cause &= ~CAUSEF_BD;*/
|
|
|
|
if (xcp->cp0_cause & CAUSEF_BD) {
|
|
|
|
/* The instruction to be emulated is in a branch delay slot
|
|
* which means that we have to emulate the branch instruction
|
|
* BEFORE we do the emulating instruction.
|
|
* This branch could be a COP1 branch
|
|
*/
|
|
|
|
emulpc = REG_TO_VA_l(xcp->cp0_epc + 4); /* Snapshot emulation target */
|
|
|
|
#ifndef __bjzheng__
|
|
if( __compute_return_epc(xcp)) {/*compute the return address*/
|
|
#ifdef DBG
|
|
_mon_printf ("failed to emulate branch at %p\n",
|
|
REG_TO_VA_l (xcp->cp0_epc));
|
|
#endif
|
|
return -1;;
|
|
}
|
|
#endif
|
|
|
|
ir = mips_get_word_l(xcp, emulpc, &err);
|
|
if (err) {
|
|
return SIGBUS;
|
|
}
|
|
contpc = REG_TO_VA_l xcp->cp0_epc;
|
|
|
|
} else { /* not in the Branch delay slot*/
|
|
emulpc = REG_TO_VA_l xcp->cp0_epc;
|
|
contpc = REG_TO_VA_l xcp->cp0_epc + 4;
|
|
}
|
|
|
|
switch(MIPSInst_OPCODE(ir)) {
|
|
case lwl_op: /*lwl instruction*/
|
|
sig = emu_lwl(xcp,ir,emulpc);
|
|
if( sig!=0) { /*emul has failed*/
|
|
return sig;
|
|
}
|
|
break;
|
|
|
|
case lwr_op:/*lwr instruction*/
|
|
sig = emu_lwr(xcp,ir,emulpc);
|
|
if ( sig != 0){
|
|
/*emulate has failed!\n");*/
|
|
return sig;
|
|
}
|
|
break;
|
|
|
|
case swl_op:
|
|
sig = emu_swl(xcp,ir,emulpc);
|
|
if( sig!=0 ) { /*emul has failed!*/
|
|
printf("emu_swl error\r\n");
|
|
return sig;
|
|
}
|
|
break;
|
|
|
|
case swr_op:
|
|
sig = emu_swr(xcp,ir,emulpc);
|
|
if( sig!=0 ) { /*emul has failed!*/
|
|
printf("emu_swr error\r\n");
|
|
return sig;
|
|
}
|
|
break;
|
|
case spec_op:
|
|
switch (MIPSInst_FUNC(ir)){
|
|
case div_op:/*div_op*/
|
|
sig = emu_div(xcp,ir);
|
|
if(sig) {
|
|
return sig;
|
|
}
|
|
break;
|
|
case divu_op:/* divu_op:*/
|
|
sig = emu_divu(xcp,ir);
|
|
if(sig) {
|
|
return sig;
|
|
}
|
|
break;
|
|
default:;
|
|
|
|
}
|
|
|
|
default:;
|
|
}
|
|
|
|
|
|
/*we do it*/
|
|
xcp->cp0_epc = VA_TO_REG_l(contpc);
|
|
xcp->cp0_cause &= ~CAUSEF_BD;
|
|
return sig;
|
|
|
|
}
|
|
|
|
|