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@ -24,9 +24,6 @@ |
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* ARM doc DDI0403C. |
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* ARM doc DDI0403C. |
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* |
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* |
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* Also supports Cortex-M0 / ARMv6-M |
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* Also supports Cortex-M0 / ARMv6-M |
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* |
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* Issues: |
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* There are way too many magic numbers used here. |
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*/ |
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*/ |
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#include "general.h" |
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#include "general.h" |
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#include "exception.h" |
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#include "exception.h" |
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@ -421,16 +418,12 @@ static uint32_t cortexm_pc_read(target *t) |
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{ |
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{ |
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target_mem_write32(t, CORTEXM_DCRSR, 0x0F); |
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target_mem_write32(t, CORTEXM_DCRSR, 0x0F); |
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return target_mem_read32(t, CORTEXM_DCRDR); |
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return target_mem_read32(t, CORTEXM_DCRDR); |
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return 0; |
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} |
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} |
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int cortexm_pc_write(target *t, const uint32_t val) |
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static void cortexm_pc_write(target *t, const uint32_t val) |
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{ |
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{ |
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target_mem_write32(t, CORTEXM_DCRDR, val); |
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target_mem_write32(t, CORTEXM_DCRDR, val); |
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target_mem_write32(t, CORTEXM_DCRSR, CORTEXM_DCRSR_REGWnR | 0x0F); |
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target_mem_write32(t, CORTEXM_DCRSR, CORTEXM_DCRSR_REGWnR | 0x0F); |
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return 0; |
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} |
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} |
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/* The following three routines implement target halt/resume
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/* The following three routines implement target halt/resume
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