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@ -72,13 +72,13 @@ |
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to regain control of the target after the option byte reload. |
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stm32l0_option_write(t, 0x1ff80000, 0xffff0000); |
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adiv5_ap_mem_write(ap, STM32L0_NVM_PECR, STM32L0_NVM_PECR_OBL_LAUNCH); |
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|
target_mem_write32(target, STM32L0_NVM_PECR, STM32L0_NVM_PECR_OBL_LAUNCH); |
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stm32l0_option_write(t, 0x1ff80000, 0xff5500aa); |
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adiv5_ap_mem_write(ap, STM32L0_NVM_PECR, STM32L0_NVM_PECR_OBL_LAUNCH); |
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|
target_mem_write32(target, STM32L0_NVM_PECR, STM32L0_NVM_PECR_OBL_LAUNCH); |
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uint32_t sr; |
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do { |
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sr = adiv5_ap_mem_read(ap, STM32L0_NVM_SR); |
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sr = target_mem_read32(target, STM32L0_NVM_SR); |
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} while (sr & STM32L0_NVM_SR_BSY); |
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|
o Errors. We probably should clear SR errors immediately after |
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|
@ -288,7 +288,7 @@ bool stm32l0_probe(struct target_s* target) |
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#if defined(CONFIG_STM32L1) |
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idcode = adiv5_ap_mem_read(adiv5_target_ap(target), |
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|
idcode = target_mem_read32(target, |
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STM32L1_DBGMCU_IDCODE_PHYS) & 0xfff; |
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switch (idcode) { |
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|
case 0x416: /* CAT. 1 device */ |
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@ -306,7 +306,7 @@ bool stm32l0_probe(struct target_s* target) |
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} |
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#endif |
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idcode = adiv5_ap_mem_read(adiv5_target_ap(target), |
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|
idcode = target_mem_read32(target, |
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STM32L0_DBGMCU_IDCODE_PHYS) & 0xfff; |
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switch (idcode) { |
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default: |
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@ -327,42 +327,42 @@ bool stm32l0_probe(struct target_s* target) |
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/** Lock the NVM control registers preventing writes or erases. */ |
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static void stm32lx_nvm_lock(ADIv5_AP_t* ap, uint32_t nvm) |
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|
static void stm32lx_nvm_lock(target *t, uint32_t nvm) |
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{ |
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|
adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_PELOCK); |
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target_mem_write32(t, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_PELOCK); |
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|
} |
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|
/** Unlock the NVM control registers for modifying program or
|
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|
data flash. Returns true if the unlock succeeds. */ |
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|
static bool stm32lx_nvm_prog_data_unlock(ADIv5_AP_t* ap, uint32_t nvm) |
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|
static bool stm32lx_nvm_prog_data_unlock(target* t, uint32_t nvm) |
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|
{ |
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|
/* Always lock first because that's the only way to know that the
|
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|
unlock can succeed on the STM32L0's. */ |
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|
adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_PELOCK); |
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|
adiv5_ap_mem_write(ap, STM32Lx_NVM_PEKEYR(nvm), STM32Lx_NVM_PEKEY1); |
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|
adiv5_ap_mem_write(ap, STM32Lx_NVM_PEKEYR(nvm), STM32Lx_NVM_PEKEY2); |
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|
adiv5_ap_mem_write(ap, STM32Lx_NVM_PRGKEYR(nvm), STM32Lx_NVM_PRGKEY1); |
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|
adiv5_ap_mem_write(ap, STM32Lx_NVM_PRGKEYR(nvm), STM32Lx_NVM_PRGKEY2); |
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|
target_mem_write32(t, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_PELOCK); |
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|
target_mem_write32(t, STM32Lx_NVM_PEKEYR(nvm), STM32Lx_NVM_PEKEY1); |
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|
target_mem_write32(t, STM32Lx_NVM_PEKEYR(nvm), STM32Lx_NVM_PEKEY2); |
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|
|
target_mem_write32(t, STM32Lx_NVM_PRGKEYR(nvm), STM32Lx_NVM_PRGKEY1); |
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|
target_mem_write32(t, STM32Lx_NVM_PRGKEYR(nvm), STM32Lx_NVM_PRGKEY2); |
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|
return !(adiv5_ap_mem_read(ap, STM32Lx_NVM_PECR(nvm)) |
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|
return !(target_mem_read32(t, STM32Lx_NVM_PECR(nvm)) |
|
|
|
& STM32Lx_NVM_PECR_PRGLOCK); |
|
|
|
} |
|
|
|
|
|
|
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|
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|
|
/** Unlock the NVM control registers for modifying option bytes.
|
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|
|
Returns true if the unlock succeeds. */ |
|
|
|
static bool stm32lx_nvm_opt_unlock(ADIv5_AP_t* ap, uint32_t nvm) |
|
|
|
static bool stm32lx_nvm_opt_unlock(target *t, uint32_t nvm) |
|
|
|
{ |
|
|
|
/* Always lock first because that's the only way to know that the
|
|
|
|
unlock can succeed on the STM32L0's. */ |
|
|
|
adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_PELOCK); |
|
|
|
adiv5_ap_mem_write(ap, STM32Lx_NVM_PEKEYR(nvm), STM32Lx_NVM_PEKEY1); |
|
|
|
adiv5_ap_mem_write(ap, STM32Lx_NVM_PEKEYR(nvm), STM32Lx_NVM_PEKEY2); |
|
|
|
adiv5_ap_mem_write(ap, STM32Lx_NVM_OPTKEYR(nvm), STM32Lx_NVM_OPTKEY1); |
|
|
|
adiv5_ap_mem_write(ap, STM32Lx_NVM_OPTKEYR(nvm), STM32Lx_NVM_OPTKEY2); |
|
|
|
target_mem_write32(t, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_PELOCK); |
|
|
|
target_mem_write32(t, STM32Lx_NVM_PEKEYR(nvm), STM32Lx_NVM_PEKEY1); |
|
|
|
target_mem_write32(t, STM32Lx_NVM_PEKEYR(nvm), STM32Lx_NVM_PEKEY2); |
|
|
|
target_mem_write32(t, STM32Lx_NVM_OPTKEYR(nvm), STM32Lx_NVM_OPTKEY1); |
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|
|
target_mem_write32(t, STM32Lx_NVM_OPTKEYR(nvm), STM32Lx_NVM_OPTKEY2); |
|
|
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|
|
|
|
return !(adiv5_ap_mem_read(ap, STM32Lx_NVM_PECR(nvm)) |
|
|
|
return !(target_mem_read32(t, STM32Lx_NVM_PECR(nvm)) |
|
|
|
& STM32Lx_NVM_PECR_OPTLOCK); |
|
|
|
} |
|
|
|
|
|
|
|
@ -400,8 +400,7 @@ static int stm32lx_nvm_prog_erase_stubbed(struct target_s* target, |
|
|
|
while (!target_halt_wait(target)) |
|
|
|
; |
|
|
|
{ |
|
|
|
ADIv5_AP_t* ap = adiv5_target_ap(target); |
|
|
|
if (adiv5_ap_mem_read(ap, STM32Lx_NVM_SR(nvm)) |
|
|
|
if (target_mem_read32(target, STM32Lx_NVM_SR(nvm)) |
|
|
|
& STM32Lx_NVM_SR_ERR_M) |
|
|
|
return -1; |
|
|
|
} |
|
|
|
@ -477,8 +476,7 @@ static int stm32lx_nvm_prog_write_stubbed(struct target_s* target, |
|
|
|
while (!target_halt_wait(target)) |
|
|
|
; |
|
|
|
|
|
|
|
if (adiv5_ap_mem_read(adiv5_target_ap(target), |
|
|
|
STM32Lx_NVM_SR(nvm)) |
|
|
|
if (target_mem_read32(target, STM32Lx_NVM_SR(nvm)) |
|
|
|
& STM32Lx_NVM_SR_ERR_M) |
|
|
|
return -1; |
|
|
|
} |
|
|
|
@ -557,7 +555,6 @@ static int stm32lx_nvm_write(struct target_s* target, |
|
|
|
static int stm32lx_nvm_prog_erase(struct target_s* target, |
|
|
|
uint32_t addr, size_t len) |
|
|
|
{ |
|
|
|
ADIv5_AP_t* ap = adiv5_target_ap(target); |
|
|
|
const size_t page_size = stm32lx_nvm_prog_page_size(target); |
|
|
|
const uint32_t nvm = stm32lx_nvm_phys(target); |
|
|
|
|
|
|
|
@ -565,15 +562,15 @@ static int stm32lx_nvm_prog_erase(struct target_s* target, |
|
|
|
len += (addr & 3); |
|
|
|
addr &= ~3; |
|
|
|
|
|
|
|
if (!stm32lx_nvm_prog_data_unlock(ap, nvm)) |
|
|
|
if (!stm32lx_nvm_prog_data_unlock(target, nvm)) |
|
|
|
return -1; |
|
|
|
|
|
|
|
/* Flash page erase instruction */ |
|
|
|
adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), |
|
|
|
target_mem_write32(target, STM32Lx_NVM_PECR(nvm), |
|
|
|
STM32Lx_NVM_PECR_ERASE | STM32Lx_NVM_PECR_PROG); |
|
|
|
|
|
|
|
{ |
|
|
|
uint32_t pecr = adiv5_ap_mem_read(ap, STM32Lx_NVM_PECR(nvm)); |
|
|
|
uint32_t pecr = target_mem_read32(target, STM32Lx_NVM_PECR(nvm)); |
|
|
|
if ((pecr & (STM32Lx_NVM_PECR_PROG | STM32Lx_NVM_PECR_ERASE)) |
|
|
|
!= (STM32Lx_NVM_PECR_PROG | STM32Lx_NVM_PECR_ERASE)) |
|
|
|
return -1; |
|
|
|
@ -581,22 +578,22 @@ static int stm32lx_nvm_prog_erase(struct target_s* target, |
|
|
|
|
|
|
|
/* Clear errors. Note that this only works when we wait for the NVM
|
|
|
|
block to complete the last operation. */ |
|
|
|
adiv5_ap_mem_write(ap, STM32Lx_NVM_SR(nvm), STM32Lx_NVM_SR_ERR_M); |
|
|
|
target_mem_write32(target, STM32Lx_NVM_SR(nvm), STM32Lx_NVM_SR_ERR_M); |
|
|
|
|
|
|
|
while (len > 0) { |
|
|
|
/* Write first word of page to 0 */ |
|
|
|
adiv5_ap_mem_write(ap, addr, 0); |
|
|
|
target_mem_write32(target, addr, 0); |
|
|
|
|
|
|
|
len -= page_size; |
|
|
|
addr += page_size; |
|
|
|
} |
|
|
|
|
|
|
|
/* Disable further programming by locking PECR */ |
|
|
|
stm32lx_nvm_lock(ap, nvm); |
|
|
|
stm32lx_nvm_lock(target, nvm); |
|
|
|
|
|
|
|
/* Wait for completion or an error */ |
|
|
|
while (1) { |
|
|
|
uint32_t sr = adiv5_ap_mem_read(ap, STM32Lx_NVM_SR(nvm)); |
|
|
|
uint32_t sr = target_mem_read32(target, STM32Lx_NVM_SR(nvm)); |
|
|
|
if (target_check_error(target)) |
|
|
|
return -1; |
|
|
|
if (sr & STM32Lx_NVM_SR_BSY) |
|
|
|
@ -618,7 +615,6 @@ static int stm32lx_nvm_prog_write(struct target_s* target, |
|
|
|
const uint8_t* source_8, |
|
|
|
size_t size) |
|
|
|
{ |
|
|
|
ADIv5_AP_t* ap = adiv5_target_ap(target); |
|
|
|
const uint32_t nvm = stm32lx_nvm_phys(target); |
|
|
|
const bool is_stm32l1 = stm32lx_is_stm32l1(target); |
|
|
|
|
|
|
|
@ -629,7 +625,7 @@ static int stm32lx_nvm_prog_write(struct target_s* target, |
|
|
|
if ((destination & 3) || (size & 3)) |
|
|
|
return -1; |
|
|
|
|
|
|
|
if (!stm32lx_nvm_prog_data_unlock(ap, nvm)) |
|
|
|
if (!stm32lx_nvm_prog_data_unlock(target, nvm)) |
|
|
|
return -1; |
|
|
|
|
|
|
|
const size_t half_page_size = stm32lx_nvm_prog_page_size(target)/2; |
|
|
|
@ -639,7 +635,7 @@ static int stm32lx_nvm_prog_write(struct target_s* target, |
|
|
|
|
|
|
|
/* Wait for BSY to clear because we cannot write the PECR until
|
|
|
|
the previous operation completes on STM32Lxxx. */ |
|
|
|
while (adiv5_ap_mem_read(ap, STM32Lx_NVM_SR(nvm)) |
|
|
|
while (target_mem_read32(target, STM32Lx_NVM_SR(nvm)) |
|
|
|
& STM32Lx_NVM_SR_BSY) |
|
|
|
if (target_check_error(target)) { |
|
|
|
return -1; |
|
|
|
@ -649,7 +645,7 @@ static int stm32lx_nvm_prog_write(struct target_s* target, |
|
|
|
// than a half page to write
|
|
|
|
if (size < half_page_size |
|
|
|
|| (destination & (half_page_size - 1))) { |
|
|
|
adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), |
|
|
|
target_mem_write32(target, STM32Lx_NVM_PECR(nvm), |
|
|
|
is_stm32l1 |
|
|
|
? 0 |
|
|
|
: STM32Lx_NVM_PECR_PROG); |
|
|
|
@ -666,7 +662,7 @@ static int stm32lx_nvm_prog_write(struct target_s* target, |
|
|
|
} |
|
|
|
// Or we are writing a half-page(s)
|
|
|
|
else { |
|
|
|
adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), |
|
|
|
target_mem_write32(target, STM32Lx_NVM_PECR(nvm), |
|
|
|
STM32Lx_NVM_PECR_PROG |
|
|
|
| STM32Lx_NVM_PECR_FPRG); |
|
|
|
|
|
|
|
@ -679,11 +675,11 @@ static int stm32lx_nvm_prog_write(struct target_s* target, |
|
|
|
} |
|
|
|
|
|
|
|
/* Disable further programming by locking PECR */ |
|
|
|
stm32lx_nvm_lock(ap, nvm); |
|
|
|
stm32lx_nvm_lock(target, nvm); |
|
|
|
|
|
|
|
/* Wait for completion or an error */ |
|
|
|
while (1) { |
|
|
|
uint32_t sr = adiv5_ap_mem_read(ap, STM32Lx_NVM_SR(nvm)); |
|
|
|
uint32_t sr = target_mem_read32(target, STM32Lx_NVM_SR(nvm)); |
|
|
|
if (target_check_error(target)) { |
|
|
|
return -1; |
|
|
|
} |
|
|
|
@ -706,7 +702,6 @@ static int stm32lx_nvm_prog_write(struct target_s* target, |
|
|
|
static int stm32lx_nvm_data_erase(struct target_s* target, |
|
|
|
uint32_t addr, size_t len) |
|
|
|
{ |
|
|
|
ADIv5_AP_t* ap = adiv5_target_ap(target); |
|
|
|
const size_t page_size = stm32lx_nvm_data_page_size(target); |
|
|
|
const uint32_t nvm = stm32lx_nvm_phys(target); |
|
|
|
|
|
|
|
@ -714,15 +709,15 @@ static int stm32lx_nvm_data_erase(struct target_s* target, |
|
|
|
len += (addr & 3); |
|
|
|
addr &= ~3; |
|
|
|
|
|
|
|
if (!stm32lx_nvm_prog_data_unlock(ap, nvm)) |
|
|
|
if (!stm32lx_nvm_prog_data_unlock(target, nvm)) |
|
|
|
return -1; |
|
|
|
|
|
|
|
/* Flash data erase instruction */ |
|
|
|
adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), |
|
|
|
target_mem_write32(target, STM32Lx_NVM_PECR(nvm), |
|
|
|
STM32Lx_NVM_PECR_ERASE | STM32Lx_NVM_PECR_DATA); |
|
|
|
|
|
|
|
{ |
|
|
|
uint32_t pecr = adiv5_ap_mem_read(ap, STM32Lx_NVM_PECR(nvm)); |
|
|
|
uint32_t pecr = target_mem_read32(target, STM32Lx_NVM_PECR(nvm)); |
|
|
|
if ((pecr & (STM32Lx_NVM_PECR_ERASE | STM32Lx_NVM_PECR_DATA)) |
|
|
|
!= (STM32Lx_NVM_PECR_ERASE | STM32Lx_NVM_PECR_DATA)) |
|
|
|
return -1; |
|
|
|
@ -730,18 +725,18 @@ static int stm32lx_nvm_data_erase(struct target_s* target, |
|
|
|
|
|
|
|
while (len > 0) { |
|
|
|
/* Write first word of page to 0 */ |
|
|
|
adiv5_ap_mem_write(ap, addr, 0); |
|
|
|
target_mem_write32(target, addr, 0); |
|
|
|
|
|
|
|
len -= page_size; |
|
|
|
addr += page_size; |
|
|
|
} |
|
|
|
|
|
|
|
/* Disable further programming by locking PECR */ |
|
|
|
stm32lx_nvm_lock(ap, nvm); |
|
|
|
stm32lx_nvm_lock(target, nvm); |
|
|
|
|
|
|
|
/* Wait for completion or an error */ |
|
|
|
while (1) { |
|
|
|
uint32_t sr = adiv5_ap_mem_read(ap, STM32Lx_NVM_SR(nvm)); |
|
|
|
uint32_t sr = target_mem_read32(target, STM32Lx_NVM_SR(nvm)); |
|
|
|
if (target_check_error(target)) |
|
|
|
return -1; |
|
|
|
if (sr & STM32Lx_NVM_SR_BSY) |
|
|
|
@ -764,22 +759,21 @@ static int stm32lx_nvm_data_write(struct target_s* target, |
|
|
|
const uint8_t* source_8, |
|
|
|
size_t size) |
|
|
|
{ |
|
|
|
ADIv5_AP_t* ap = adiv5_target_ap(target); |
|
|
|
const uint32_t nvm = stm32lx_nvm_phys(target); |
|
|
|
const bool is_stm32l1 = stm32lx_is_stm32l1(target); |
|
|
|
uint32_t* source = (uint32_t*) source_8; |
|
|
|
|
|
|
|
if (!stm32lx_nvm_prog_data_unlock(ap, nvm)) |
|
|
|
if (!stm32lx_nvm_prog_data_unlock(target, nvm)) |
|
|
|
return -1; |
|
|
|
|
|
|
|
|
|
|
|
adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), |
|
|
|
target_mem_write32(target, STM32Lx_NVM_PECR(nvm), |
|
|
|
is_stm32l1 ? 0 : STM32Lx_NVM_PECR_DATA); |
|
|
|
|
|
|
|
while (size) { |
|
|
|
size -= 4; |
|
|
|
uint32_t v = *source++; |
|
|
|
adiv5_ap_mem_write(ap, destination, v); |
|
|
|
target_mem_write32(target, destination, v); |
|
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destination += 4; |
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if (target_check_error(target)) |
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@ -787,11 +781,11 @@ static int stm32lx_nvm_data_write(struct target_s* target, |
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} |
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/* Disable further programming by locking PECR */ |
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stm32lx_nvm_lock(ap, nvm); |
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stm32lx_nvm_lock(target, nvm); |
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/* Wait for completion or an error */ |
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while (1) { |
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uint32_t sr = adiv5_ap_mem_read(ap, STM32Lx_NVM_SR(nvm)); |
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uint32_t sr = target_mem_read32(target, STM32Lx_NVM_SR(nvm)); |
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if (target_check_error(target)) |
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return -1; |
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if (sr & STM32Lx_NVM_SR_BSY) |
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@ -813,16 +807,15 @@ static int stm32lx_nvm_data_write(struct target_s* target, |
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The return value is true if the write succeeded. */ |
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static bool stm32lx_option_write(target *t, uint32_t address, uint32_t value) |
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{ |
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ADIv5_AP_t* ap = adiv5_target_ap(t); |
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const uint32_t nvm = stm32lx_nvm_phys(t); |
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/* Erase and program option in one go. */ |
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adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_FIX); |
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adiv5_ap_mem_write(ap, address, value); |
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target_mem_write32(t, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_FIX); |
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target_mem_write32(t, address, value); |
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uint32_t sr; |
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do { |
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sr = adiv5_ap_mem_read(ap, STM32Lx_NVM_SR(nvm)); |
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sr = target_mem_read32(t, STM32Lx_NVM_SR(nvm)); |
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} while (sr & STM32Lx_NVM_SR_BSY); |
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return !(sr & STM32Lx_NVM_SR_ERR_M); |
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@ -839,29 +832,28 @@ static bool stm32lx_option_write(target *t, uint32_t address, uint32_t value) |
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static bool stm32lx_eeprom_write(target *t, uint32_t address, |
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size_t cb, uint32_t value) |
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{ |
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ADIv5_AP_t* ap = adiv5_target_ap(t); |
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const uint32_t nvm = stm32lx_nvm_phys(t); |
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const bool is_stm32l1 = stm32lx_is_stm32l1(t); |
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/* Clear errors. */ |
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adiv5_ap_mem_write(ap, STM32Lx_NVM_SR(nvm), STM32Lx_NVM_SR_ERR_M); |
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target_mem_write32(t, STM32Lx_NVM_SR(nvm), STM32Lx_NVM_SR_ERR_M); |
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/* Erase and program option in one go. */ |
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adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), |
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target_mem_write32(t, STM32Lx_NVM_PECR(nvm), |
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(is_stm32l1 ? 0 : STM32Lx_NVM_PECR_DATA) |
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| STM32Lx_NVM_PECR_FIX); |
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if (cb == 4) |
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adiv5_ap_mem_write(ap, address, value); |
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target_mem_write32(t, address, value); |
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else if (cb == 2) |
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adiv5_ap_mem_write_halfword(ap, address, value); |
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target_mem_write16(t, address, value); |
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else if (cb == 1) |
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adiv5_ap_mem_write_byte(ap, address, value); |
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target_mem_write8(t, address, value); |
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else |
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return false; |
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uint32_t sr; |
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do { |
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sr = adiv5_ap_mem_read(ap, STM32Lx_NVM_SR(nvm)); |
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sr = target_mem_read32(t, STM32Lx_NVM_SR(nvm)); |
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} while (sr & STM32Lx_NVM_SR_BSY); |
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return !(sr & STM32Lx_NVM_SR_ERR_M); |
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@ -888,11 +880,10 @@ static bool stm32lx_cmd_stubs(target* t, |
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static bool stm32lx_cmd_option(target* t, int argc, char** argv) |
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{ |
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ADIv5_AP_t* ap = adiv5_target_ap(t); |
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const uint32_t nvm = stm32lx_nvm_phys(t); |
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const size_t opt_size = stm32lx_nvm_option_size(t); |
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if (!stm32lx_nvm_opt_unlock(ap, nvm)) { |
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if (!stm32lx_nvm_opt_unlock(t, nvm)) { |
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gdb_out("unable to unlock NVM option bytes\n"); |
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return true; |
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} |
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@ -900,7 +891,7 @@ static bool stm32lx_cmd_option(target* t, int argc, char** argv) |
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size_t cb = strlen(argv[1]); |
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if (argc == 2 && !strncasecmp(argv[1], "obl_launch", cb)) { |
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adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), |
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target_mem_write32(t, STM32Lx_NVM_PECR(nvm), |
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STM32Lx_NVM_PECR_OBL_LAUNCH); |
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} |
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else if (argc == 4 && !strncasecmp(argv[1], "raw", cb)) { |
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@ -934,7 +925,7 @@ static bool stm32lx_cmd_option(target* t, int argc, char** argv) |
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/* Report the current option values */ |
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for(unsigned i = 0; i < opt_size; i += sizeof(uint32_t)) { |
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uint32_t addr = STM32Lx_NVM_OPT_PHYS + i; |
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uint32_t val = adiv5_ap_mem_read(ap, addr); |
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uint32_t val = target_mem_read32(t, addr); |
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gdb_outf("0x%08x: 0x%04x 0x%04x %s\n", |
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addr, val & 0xffff, (val >> 16) & 0xffff, |
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((val & 0xffff) == ((~val >> 16) & 0xffff)) |
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@ -942,7 +933,7 @@ static bool stm32lx_cmd_option(target* t, int argc, char** argv) |
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} |
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if (stm32lx_is_stm32l1(t)) { |
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uint32_t optr = adiv5_ap_mem_read(ap, STM32Lx_NVM_OPTR(nvm)); |
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uint32_t optr = target_mem_read32(t, STM32Lx_NVM_OPTR(nvm)); |
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uint8_t rdprot = (optr >> STM32L1_NVM_OPTR_RDPROT_S) |
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& STM32L1_NVM_OPTR_RDPROT_M; |
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if (rdprot == STM32L1_NVM_OPTR_RDPROT_0) |
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@ -964,7 +955,7 @@ static bool stm32lx_cmd_option(target* t, int argc, char** argv) |
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(optr & STM32L1_NVM_OPTR_nBFB2) ? 1 : 0); |
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} |
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else { |
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uint32_t optr = adiv5_ap_mem_read(ap, STM32Lx_NVM_OPTR(nvm)); |
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uint32_t optr = target_mem_read32(t, STM32Lx_NVM_OPTR(nvm)); |
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uint8_t rdprot = (optr >> STM32L0_NVM_OPTR_RDPROT_S) |
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& STM32L0_NVM_OPTR_RDPROT_M; |
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if (rdprot == STM32L0_NVM_OPTR_RDPROT_0) |
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@ -997,17 +988,16 @@ usage: |
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STM32Lx_NVM_OPT_PHYS + opt_size - sizeof(uint32_t)); |
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done: |
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stm32lx_nvm_lock(ap, nvm); |
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stm32lx_nvm_lock(t, nvm); |
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return true; |
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} |
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static bool stm32lx_cmd_eeprom(target* t, int argc, char** argv) |
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{ |
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ADIv5_AP_t* ap = adiv5_target_ap(t); |
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const uint32_t nvm = stm32lx_nvm_phys(t); |
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if (!stm32lx_nvm_prog_data_unlock(ap, nvm)) { |
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if (!stm32lx_nvm_prog_data_unlock(t, nvm)) { |
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gdb_out("unable to unlock EEPROM\n"); |
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return true; |
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} |
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@ -1061,6 +1051,6 @@ usage: |
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+ stm32lx_nvm_eeprom_size(t)); |
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done: |
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stm32lx_nvm_lock(ap, nvm); |
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stm32lx_nvm_lock(t, nvm); |
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return true; |
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} |
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Gareth McMullin
10 years ago