misc: Renamed CORTEXM_TOPT_INHIBIT_NRST to clarify usage and align naming

src/target/cortexm.c

@@ -742,7 +742,7 @@ static void cortexm_reset(target *t)
 	/* Read DHCSR here to clear S_RESET_ST bit before reset */
 	target_mem_read32(t, CORTEXM_DHCSR);
 	platform_timeout to;
-	if ((t->target_options & CORTEXM_TOPT_INHIBIT_SRST) == 0) {
+	if ((t->target_options & CORTEXM_TOPT_INHIBIT_NRST) == 0) {
 		platform_nrst_set_val(true);
 		platform_nrst_set_val(false);
 		/* Some NRF52840 users saw invalid SWD transaction with
@@ -752,7 +752,7 @@ static void cortexm_reset(target *t)
 	uint32_t dhcsr = target_mem_read32(t, CORTEXM_DHCSR);
 	if ((dhcsr & CORTEXM_DHCSR_S_RESET_ST) == 0) {
 		/* No reset seen yet, maybe as nRST is not connected, or device has
-         * CORTEXM_TOPT_INHIBIT_SRST set.
+         * CORTEXM_TOPT_INHIBIT_NRST set.
 		 * Trigger reset by AIRCR.*/
 		target_mem_write32(t, CORTEXM_AIRCR,
 						   CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_SYSRESETREQ);

src/target/cortexm.h

@@ -170,7 +170,7 @@ extern unsigned cortexm_wait_timeout;
 #define ARM_THUMB_BREAKPOINT 0xBE00
 #define CORTEXM_XPSR_THUMB (1 << 24)
 
-#define	CORTEXM_TOPT_INHIBIT_SRST (1 << 2)
+#define	CORTEXM_TOPT_INHIBIT_NRST (1 << 2)
 
 enum cortexm_types {
 	CORTEX_M0  = 0xc200,
@@ -196,4 +196,3 @@ int cortexm_mem_write_sized(
 	target *t, target_addr dest, const void *src, size_t len, enum align align);
 
 #endif
-

src/target/efm32.c

@@ -648,7 +648,7 @@ bool efm32_probe(target *t)
 			device->name, part_number, flash_kib, device->description);
 
 	/* Setup Target */
-	t->target_options |= CORTEXM_TOPT_INHIBIT_SRST;
+	t->target_options |= CORTEXM_TOPT_INHIBIT_NRST;
 	t->driver = priv_storage->efm32_variant_string;
 	tc_printf(t, "flash size %d page size %d\n", flash_size, flash_page_size);
 	target_add_ram (t, SRAM_BASE, ram_size);

src/target/lmi.c

@@ -91,21 +91,21 @@ bool lmi_probe(target *t)
 		/* On Tiva targets, asserting nRST results in the debug
 		 * logic also being reset.  We can't assert nRST and must
 		 * only use the AIRCR SYSRESETREQ. */
-		t->target_options |= CORTEXM_TOPT_INHIBIT_SRST;
+		t->target_options |= CORTEXM_TOPT_INHIBIT_NRST;
 		return true;
 
 	case 0x1022:    /* TM4C1230C3PM */
 		t->driver = lmi_driver_str;
 		target_add_ram(t, 0x20000000, 0x6000);
 		lmi_add_flash(t, 0x10000);
-		t->target_options |= CORTEXM_TOPT_INHIBIT_SRST;
+		t->target_options |= CORTEXM_TOPT_INHIBIT_NRST;
 		return true;
 
 	case 0x101F:    /* TM4C1294NCPDT */
 		t->driver = lmi_driver_str;
 		target_add_ram(t, 0x20000000, 0x40000);
 		lmi_add_flash(t, 0x100000);
-		t->target_options |= CORTEXM_TOPT_INHIBIT_SRST;
+		t->target_options |= CORTEXM_TOPT_INHIBIT_NRST;
 		return true;
 	}
 	return false;

src/target/lpc43xx.c

@@ -107,7 +107,7 @@ bool lpc43xx_probe(target *t)
 				                  0x1B010000, 0x70000, 0x10000);
 				target_add_commands(t, lpc43xx_cmd_list, "LPC43xx");
 				target_add_ram(t, 0x1B080000, 0xE4F80000UL);
-				t->target_options |= CORTEXM_TOPT_INHIBIT_SRST;
+				t->target_options |= CORTEXM_TOPT_INHIBIT_NRST;
 			}
 			break;
 		case 0x4100C200:
@@ -262,4 +262,3 @@ static void lpc43xx_wdt_pet(target *t)
 		target_mem_write32(t, LPC43XX_WDT_FEED, 0xFF);
 	}
 }
-

src/target/lpc546xx.c

@@ -161,7 +161,7 @@ bool lpc546xx_probe(target *t)
 	*/
 	target_add_ram(t, 0x20000000, 0x28000);
 	target_add_commands(t, lpc546xx_cmd_list, "Lpc546xx");
-	t->target_options |= CORTEXM_TOPT_INHIBIT_SRST;
+	t->target_options |= CORTEXM_TOPT_INHIBIT_NRST;
 
 	return true;
 }

src/target/nrf51.c

@@ -135,7 +135,7 @@ bool nrf51_probe(target *t)
 		((info_part & 0x00ff000) == 0x52000)) {
 		uint32_t ram_size = target_mem_read32(t, NRF52_INFO_RAM);
 		t->driver = "Nordic nRF52";
-		t->target_options |= CORTEXM_TOPT_INHIBIT_SRST;
+		t->target_options |= CORTEXM_TOPT_INHIBIT_NRST;
 		target_add_ram(t, 0x20000000, ram_size * 1024);
 		nrf51_add_flash(t, 0, page_size * code_size, page_size);
 		nrf51_add_flash(t, NRF51_UICR, page_size, page_size);
@@ -147,7 +147,7 @@ bool nrf51_probe(target *t)
 		 * IDCODE is kept as '0', as deciphering is hard and
 		 * there is later no usage.*/
 		target_add_ram(t, 0x20000000, 0x8000);
-		t->target_options |= CORTEXM_TOPT_INHIBIT_SRST;
+		t->target_options |= CORTEXM_TOPT_INHIBIT_NRST;
 		nrf51_add_flash(t, 0, page_size * code_size, page_size);
 		nrf51_add_flash(t, NRF51_UICR, page_size, page_size);
 		target_add_commands(t, nrf51_cmd_list, "nRF51");

src/target/rp.c

@@ -520,7 +520,7 @@ bool rp_probe(target *t)
  	t->target_storage = (void*)priv_storage;
 
 	t->driver = RP_ID;
-	t->target_options |= CORTEXM_TOPT_INHIBIT_SRST;
+	t->target_options |= CORTEXM_TOPT_INHIBIT_NRST;
 	t->attach = rp_attach;
 	t->detach = rp_detach;
 	target_add_commands(t, rp_cmd_list, RP_ID);