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@ -29,7 +29,10 @@ |
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#include "cortexm.h" |
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#define SRAM_BASE 0x20000000 |
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#define STUB_BUFFER_BASE (SRAM_BASE + 0x30) |
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#define BLOCK_SIZE 0x400 |
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#define LMI_SCB_BASE 0x400FE000 |
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#define LMI_SCB_DID1 (LMI_SCB_BASE + 0x004) |
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@ -73,41 +76,7 @@ static const char tm4c123gh6pm_xml_memory_map[] = "<?xml version=\"1.0\"?>" |
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static const uint16_t lmi_flash_write_stub[] = { |
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// _start:
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0x4809, // ldr r0, [pc, #36] // _flashbase
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0x490b, // ldr r1, [pc, #44] // _addr
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0x467a, // mov r2, pc
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0x3230, // adds r2, #48
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0x4b0a, // ldr r3, [pc, #40] // _size
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0x4d08, // ldr r5, [pc, #32] // _flash_write_cmd
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// _next:
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0xb15b, // cbz r3, _done
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0x6001, // str r1, [r0, #0]
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0x6814, // ldr r4, [r2]
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0x6044, // str r4, [r0, #4]
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0x6085, // str r5, [r0, #8]
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// _wait:
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0x6884, // ldr r4, [r0, #8]
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0x2601, // movs r6, #1
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0x4234, // tst r4, r6
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0xd1fb, // bne _wait
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0x3b01, // subs r3, #1
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0x3104, // adds r1, #4
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0x3204, // adds r2, #4
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0xe7f2, // b _next
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// _done:
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0xbe00, // bkpt
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// _flashbase:
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0xd000, 0x400f, // .word 0x400fd000
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// _flash_write_cmd:
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0x0001, 0xa442, // .word 0xa4420001
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// _addr:
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// 0x0000, 0x0000,
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// _size:
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// 0x0000, 0x0000,
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// _data:
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// ...
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#include "../flashstub/lmi.stub" |
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}; |
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bool lmi_probe(target *t) |
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@ -155,16 +124,10 @@ int lmi_flash_write(target *t, uint32_t dest, const uint8_t *src, size_t len) |
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data[0] = dest; |
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data[1] = len >> 2; |
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memcpy(&data[2], src, len); |
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DEBUG("Sending stub\n"); |
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target_mem_write(t, SRAM_BASE, lmi_flash_write_stub, 0x30); |
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DEBUG("Sending data\n"); |
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target_mem_write(t, 0x20000030, data, len + 8); |
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DEBUG("Running stub\n"); |
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cortexm_pc_write(t, 0x20000000); |
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target_halt_resume(t, 0); |
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DEBUG("Waiting for halt\n"); |
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while(!target_halt_wait(t)); |
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return 0; |
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target_mem_write(t, SRAM_BASE, lmi_flash_write_stub, |
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sizeof(lmi_flash_write_stub)); |
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target_mem_write(t, STUB_BUFFER_BASE, data, len + 8); |
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return cortexm_run_stub(t, SRAM_BASE, 0, 0, 0, 0); |
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} |
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