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libopencm3/lib/dispatch/vector_nvic.c

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[STM32F0] Add preliminary support for the family
11 years ago
#if defined(STM32F0)
# include "../stm32/f0/vector_nvic.c"
#elif defined(STM32F1)
integrate irq2nvic_h script in buildprocess
12 years ago
# include "../stm32/f1/vector_nvic.c"
#elif defined(STM32F2)
# include "../stm32/f2/vector_nvic.c"
Added interrupts for f3, Pre_main rutine in vector_chipset, nvic.h modified to include f3.
12 years ago
#elif defined(STM32F3)
# include "../stm32/f3/vector_nvic.c"
integrate irq2nvic_h script in buildprocess
12 years ago
#elif defined(STM32F4)
# include "../stm32/f4/vector_nvic.c"
[stm32f7] Add initial support of the family, GPIO support. Most changes are noise from doxygen. Readme udpated to explain newer FP_FLAGS for m7 stm32f7 library is skipped if the toolchain doesn't support it yet.
10 years ago
#elif defined(STM32F7)
# include "../stm32/f7/vector_nvic.c"
[stm32l0] Initial support for STM32L0 architecture, Add GPIO peripheral
10 years ago
#elif defined(STM32L0)
# include "../stm32/l0/vector_nvic.c"
Enable nvic and exti support for L1 And include an example that uses it.
12 years ago
#elif defined(STM32L1)
# include "../stm32/l1/vector_nvic.c"
stm32l4: initial memorymap and vector support Values from RM0351rev1, with the correction of the duplicate TIM1_CC entry. Only stub support so far, but this opens up the beginning of build testing.
9 years ago
#elif defined(STM32L4)
# include "../stm32/l4/vector_nvic.c"
integrate irq2nvic_h script in buildprocess
12 years ago
change discriminator in efm32 series from TINYGECKO to EFM32TG
12 years ago
#elif defined(EFM32TG)
Inital support for EFM32LG
10 years ago
# include "../efm32/tg/vector_nvic.c"
added irqs for the rest of the efm32 devices
12 years ago
#elif defined(EFM32G)
Inital support for EFM32LG
10 years ago
# include "../efm32/g/vector_nvic.c"
added irqs for the rest of the efm32 devices
12 years ago
#elif defined(EFM32LG)
Inital support for EFM32LG
10 years ago
# include "../efm32/lg/vector_nvic.c"
added irqs for the rest of the efm32 devices
12 years ago
#elif defined(EFM32GG)
Inital support for EFM32LG
10 years ago
# include "../efm32/gg/vector_nvic.c"
integrate irq2nvic_h script in buildprocess
12 years ago
Added irq.yaml to lpc_13xx and lpc_17xx families
12 years ago
#elif defined(LPC13XX)
# include "../lpc13xx/vector_nvic.c"
#elif defined(LPC17XX)
# include "../lpc17xx/vector_nvic.c"
lpc43xx: Move M4 specific files to m4/
12 years ago
#elif defined(LPC43XX_M4)
# include "../lpc43xx/m4/vector_nvic.c"
lpc43xx: Add irq.yaml for M0 core
12 years ago
#elif defined(LPC43XX_M0)
# include "../lpc43xx/m0/vector_nvic.c"
integrate irq2nvic_h script in buildprocess
12 years ago
[sam3a] add irq table and memory map
11 years ago
#elif defined(SAM3A)
# include "../sam/3a/vector_nvic.c"
Split sam3x/sam3n support.
12 years ago
#elif defined(SAM3N)
# include "../sam/3n/vector_nvic.c"
add memory map and irq table for sam3s and sam3u devices
11 years ago
#elif defined(SAM3S)
# include "../sam/3s/vector_nvic.c"
#elif defined(SAM3U)
# include "../sam/3u/vector_nvic.c"
[sam3a] add irq table and memory map
11 years ago
#elif defined(SAM3X)
# include "../sam/3x/vector_nvic.c"
sam3x support.
12 years ago
vf6xx: initial add of Vybrid VF6xx support Freescale Vybrid is a familiy of ARM SoC, wheras the VF6xx models have two cores in one SoC, a Cortex-A5 and a Cortex-M4. This adds initial support for the Cortex-M4 in the libopencm3 library. By using two different ram areas (pc_ram and ps_ram) the user can put the code in a RAM area bounded to the code bus. The data can be stored in the data area. However, currently the initial values of for the variables in the data section are stored in the code section and copied to the ram section by the initialization code (like it's copied from ROM to RAM on microcontrollers).
11 years ago
#elif defined(VF6XX)
# include "../vf6xx/vector_nvic.c"
lm4f: Compile in the interrupt vector table Add an "#ifdef(LM4F)" clause to include/libopencm3/dispatch/nvic.h and lib/dispatch/vector_nvic.c. This compiles in the vector table and allows interrupts to be used. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
12 years ago
#elif defined(LM3S) || defined(LM4F)
/* Yes, we use the same interrupt table for both LM3S and LM4F */
completing dispatch the LM3S irq list was previously unused as it was missing in the dispatch files; now it got added. (before HEAD^, it wouldn't have made any difference because the discriminating constant wasn't defined anyway) also, this enhances the warning messages
12 years ago
# include "../lm3s/vector_nvic.c"
integrate irq2nvic_h script in buildprocess
12 years ago
#else
First coarse run to fix coding style in locm3. Added --terse and --mailback options to the make stylecheck target. It also does continue even if it enounters a possible error. We decided on two exceptions from the linux kernel coding standard: - Empty wait while loops may end with ; on the same line. - All blocks after while, if, for have to be in brackets even if they only contain one statement. Otherwise it is easy to introduce an error. Checkpatch needs to be adapted to reflect those changes.
12 years ago
# warning "no interrupts defined for chipset;"\
"not allocating space in the vector table"
integrate irq2nvic_h script in buildprocess
12 years ago
#define IRQ_HANDLERS
#endif