STM32F0: Fix the PLL multiplier table

The value '6' was twice in the table and all higher frequencies are
shifted. The values are now fitting the table in 'STM32F05xxx/06xxx advanced
ARM-based 32-bit MCUs', page 101.

PLL frequencies have been measured by selecting

    rcc_set_mco(RCC_CFGR_MCO_SYSCLK);

and measuring the output with an oscilloscope. 8, 16, 24, 32, 40 and 48 MHz
work fine from the HSI base.

include/libopencm3/stm32/f0/rcc.h

@@ -113,14 +113,14 @@
 #define RCC_CFGR_PLLMUL_MUL6			(0x04 << RCC_CFGR_PLLMUL_SHIFT)
 #define RCC_CFGR_PLLMUL_MUL7			(0x05 << RCC_CFGR_PLLMUL_SHIFT)
 #define RCC_CFGR_PLLMUL_MUL8			(0x06 << RCC_CFGR_PLLMUL_SHIFT)
-#define RCC_CFGR_PLLMUL_MUL9			(0x06 << RCC_CFGR_PLLMUL_SHIFT)
-#define RCC_CFGR_PLLMUL_MUL10			(0x07 << RCC_CFGR_PLLMUL_SHIFT)
-#define RCC_CFGR_PLLMUL_MUL11			(0x08 << RCC_CFGR_PLLMUL_SHIFT)
-#define RCC_CFGR_PLLMUL_MUL12			(0x09 << RCC_CFGR_PLLMUL_SHIFT)
-#define RCC_CFGR_PLLMUL_MUL13			(0x0A << RCC_CFGR_PLLMUL_SHIFT)
-#define RCC_CFGR_PLLMUL_MUL14			(0x0B << RCC_CFGR_PLLMUL_SHIFT)
-#define RCC_CFGR_PLLMUL_MUL15			(0x0C << RCC_CFGR_PLLMUL_SHIFT)
-#define RCC_CFGR_PLLMUL_MUL16			(0x0D << RCC_CFGR_PLLMUL_SHIFT)
+#define RCC_CFGR_PLLMUL_MUL9			(0x07 << RCC_CFGR_PLLMUL_SHIFT)
+#define RCC_CFGR_PLLMUL_MUL10			(0x08 << RCC_CFGR_PLLMUL_SHIFT)
+#define RCC_CFGR_PLLMUL_MUL11			(0x09 << RCC_CFGR_PLLMUL_SHIFT)
+#define RCC_CFGR_PLLMUL_MUL12			(0x0A << RCC_CFGR_PLLMUL_SHIFT)
+#define RCC_CFGR_PLLMUL_MUL13			(0x0B << RCC_CFGR_PLLMUL_SHIFT)
+#define RCC_CFGR_PLLMUL_MUL14			(0x0C << RCC_CFGR_PLLMUL_SHIFT)
+#define RCC_CFGR_PLLMUL_MUL15			(0x0D << RCC_CFGR_PLLMUL_SHIFT)
+#define RCC_CFGR_PLLMUL_MUL16			(0x0E << RCC_CFGR_PLLMUL_SHIFT)
 
 #define RCC_CFGR_PLLXTPRE			(1<<17)
 #define RCC_CFGR_PLLSRC				(1<<16)