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@ -37,7 +37,9 @@ LGPL License Terms @ref lgpl_license |
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#include <libopencm3/stm32/common/timer_common_all.h> |
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/* Timer 2/21/22 option register (TIMx_OR) */ |
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/**@{*/ |
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/** Timer 2/21/22 option register (TIMx_OR) */ |
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#define TIM_OR(tim_base) MMIO32((tim_base) + 0x50) |
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#define TIM2_OR TIM_OR(TIM2) |
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@ -115,7 +117,6 @@ LGPL License Terms @ref lgpl_license |
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#define LPTIM1_CNT LPTIM_CNT(LPTIM1_BASE) |
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/** @defgroup lptim_isr LPTIM_ISR Interrupt and Status Register
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* @ingroup timer_defines |
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@{*/ |
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#define LPTIM_ISR_CMPM (1 << 0) |
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#define LPTIM_ISR_ARRM (1 << 1) |
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@ -127,7 +128,6 @@ LGPL License Terms @ref lgpl_license |
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/**@}*/ |
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/** @defgroup lptim_icr LPTIM_ICR Interrupt Clear Register
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* @ingroup timer_defines |
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@{*/ |
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#define LPTIM_ICR_CMPMCF (1 << 0) |
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#define LPTIM_ICR_ARRMCF (1 << 1) |
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@ -139,7 +139,6 @@ LGPL License Terms @ref lgpl_license |
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/**@}*/ |
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/** @defgroup lptim_ier LPTIM_IER Interrupt Enable Register
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* @ingroup timer_defines |
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@{*/ |
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#define LPTIM_IER_CMPMIE (1 << 0) |
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#define LPTIM_IER_ARRMIE (1 << 1) |
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@ -151,7 +150,6 @@ LGPL License Terms @ref lgpl_license |
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/**@}*/ |
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/** @defgroup lptim_cfgr LPTIM_CFGR Configuration Register
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* @ingroup timer_defines |
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@{*/ |
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/** CKSEL: Select internal (0) or external clock source (1) **/ |
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@ -223,7 +221,7 @@ LGPL License Terms @ref lgpl_license |
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#define LPTIM_CFGR_TRIGEN_SHIFT 17 |
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#define LPTIM_CFGR_TRIGSEL_MASK 0x07 |
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#define LPTIM_CFGR_TRIGEN (3 << LPTIM_CFGR_TRIGEN_SHIFT) |
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/* @defgroup LPTIM_CFGR_TRIGEN LPTIM_CFGR TRIGEN Trigger enable and polarity
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/** @defgroup LPTIM_CFGR_TRIGEN LPTIM_CFGR TRIGEN Trigger enable and polarity
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@{*/ |
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#define LPTIM_CFGR_TRIGEN_SW (0 << LPTIM_CFGR_TRIGEN_SHIFT) |
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#define LPTIM_CFGR_TRIGEN_RISING (1 << LPTIM_CFGR_TRIGEN_SHIFT) |
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@ -252,7 +250,6 @@ LGPL License Terms @ref lgpl_license |
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/**@}*/ |
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/** @defgroup lptim_cr LPTIM_CR Control Register
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* @ingroup timer_defines |
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@{*/ |
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/** ENABLE: Counter enable **/ |
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@ -266,4 +263,7 @@ LGPL License Terms @ref lgpl_license |
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/**@}*/ |
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#endif |
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/**@}*/ |
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