From 10ef294e5d89a3b68a0b2d1a6d7b670c24e791aa Mon Sep 17 00:00:00 2001
From: Karl Palsson <karlp@tweak.net.au>
Date: Thu, 22 Oct 2015 22:34:29 +0000
Subject: [PATCH] stm32f3: rcc: Set prescalers properly.

Copypasta from f4 rcc code was only modified to shift the result, but not clear
the existing settings properly. Add mask/shift definitions and use them
properly.
---
 include/libopencm3/stm32/f3/rcc.h |  3 +++
 lib/stm32/f3/rcc.c                | 12 ++++++------
 2 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/include/libopencm3/stm32/f3/rcc.h b/include/libopencm3/stm32/f3/rcc.h
index a313d5eb..fa7654ec 100644
--- a/include/libopencm3/stm32/f3/rcc.h
+++ b/include/libopencm3/stm32/f3/rcc.h
@@ -124,6 +124,7 @@
 
 /* PPRE2: APB high-speed prescaler (APB2) */
 #define RCC_CFGR_PPRE2_SHIFT			11
+#define RCC_CFGR_PPRE2_MASK			0x7
 /* 0XX: HCLK not divided */
 #define RCC_CFGR_PPRE2_DIV_NONE			0x0
 
@@ -134,6 +135,7 @@
 
 /* PPRE1:APB Low-speed prescaler (APB1) */
 #define RCC_CFGR_PPRE1_SHIFT			8
+#define RCC_CFGR_PPRE1_MASK			0x7
 /* 0XX: HCLK not divided */
 #define RCC_CFGR_PPRE1_DIV_NONE			0x0
 #define RCC_CFGR_PPRE1_DIV_2			0x4
@@ -143,6 +145,7 @@
 
 /* HPRE: HLCK prescaler */
 #define RCC_CFGR_HPRE_SHIFT			4
+#define RCC_CFGR_HPRE_MASK			0xf
 /* 0XXX: SYSCLK not divided */
 #define RCC_CFGR_HPRE_DIV_NONE			0x0
 #define RCC_CFGR_HPRE_DIV_2			0x8
diff --git a/lib/stm32/f3/rcc.c b/lib/stm32/f3/rcc.c
index 69d9fb6d..6d78c283 100644
--- a/lib/stm32/f3/rcc.c
+++ b/lib/stm32/f3/rcc.c
@@ -343,8 +343,8 @@ void rcc_set_ppre2(uint32_t ppre2)
 	uint32_t reg32;
 
 	reg32 = RCC_CFGR;
-	reg32 &= ~((1 << 13) | (1 << 14) | (1 << 15));
-	RCC_CFGR = (reg32 | (ppre2 << 11));
+	reg32 &= ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_SHIFT);
+	RCC_CFGR = (reg32 | (ppre2 << RCC_CFGR_PPRE2_SHIFT));
 }
 
 void rcc_set_ppre1(uint32_t ppre1)
@@ -352,8 +352,8 @@ void rcc_set_ppre1(uint32_t ppre1)
 	uint32_t reg32;
 
 	reg32 = RCC_CFGR;
-	reg32 &= ~((1 << 10) | (1 << 11) | (1 << 12));
-	RCC_CFGR = (reg32 | (ppre1 << 8));
+	reg32 &= ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_SHIFT);
+	RCC_CFGR = (reg32 | (ppre1 << RCC_CFGR_PPRE1_SHIFT));
 }
 
 void rcc_set_hpre(uint32_t hpre)
@@ -361,8 +361,8 @@ void rcc_set_hpre(uint32_t hpre)
 	uint32_t reg32;
 
 	reg32 = RCC_CFGR;
-	reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7));
-	RCC_CFGR = (reg32 | (hpre << 4));
+	reg32 &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_SHIFT);
+	RCC_CFGR = (reg32 | (hpre << RCC_CFGR_HPRE_SHIFT));
 }