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@ -35,27 +35,6 @@ LGPL License Terms @ref lgpl_license |
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#include <libopencm3/lpc43xx/ssp.h> |
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#include <libopencm3/lpc43xx/cgu.h> |
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#define CGU_SRC_32K 0x00 |
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#define CGU_SRC_IRC 0x01 |
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#define CGU_SRC_ENET_RX 0x02 |
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#define CGU_SRC_ENET_TX 0x03 |
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#define CGU_SRC_GP_CLKIN 0x04 |
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#define CGU_SRC_XTAL 0x06 |
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#define CGU_SRC_PLL0USB 0x07 |
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#define CGU_SRC_PLL0AUDIO 0x08 |
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#define CGU_SRC_PLL1 0x09 |
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#define CGU_SRC_IDIVA 0x0C |
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#define CGU_SRC_IDIVB 0x0D |
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#define CGU_SRC_IDIVC 0x0E |
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#define CGU_SRC_IDIVD 0x0F |
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#define CGU_SRC_IDIVE 0x10 |
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#define CGU_AUTOBLOCK_CLOCK_BIT 11 |
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#define CGU_BASE_CLK_SEL_SHIFT 24 /* clock source selection (5 bits) */ |
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/* Local declarations. */ |
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void ssp_wait_until_not_busy(ssp_num_t ssp_num); |
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/* Disable SSP */ |
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void ssp_disable(ssp_num_t ssp_num) |
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{ |
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@ -93,8 +72,9 @@ void ssp_init(ssp_num_t ssp_num, |
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} |
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/* use PLL1 as clock source for SSP1 */ |
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CGU_BASE_SSP1_CLK = (CGU_SRC_PLL1<<CGU_BASE_CLK_SEL_SHIFT) | |
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(1<<CGU_AUTOBLOCK_CLOCK_BIT); |
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CGU_BASE_SSP1_CLK = |
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CGU_BASE_SSP1_CLK_CLK_SEL(CGU_SRC_PLL1) |
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| CGU_BASE_SSP1_CLK_AUTOBLOCK; |
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/* Disable SSP before to configure it */ |
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SSP_CR1(ssp_port) = 0x0; |
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