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@ -132,23 +132,27 @@ |
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/* Endpoint complete */ |
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#define USB0_ENDPTCOMPLETE MMIO32(USB0_BASE + 0x1BC) |
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/* Endpoint control */ |
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#define USB0_ENDPTCTRL(logical_ep) MMIO32(USB0_BASE + 0x1C0 + (logical_ep * 4)) |
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/* Endpoint control 0 */ |
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#define USB0_ENDPTCTRL0 MMIO32(USB0_BASE + 0x1C0) |
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#define USB0_ENDPTCTRL0 USB0_ENDPTCTRL(0) |
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/* Endpoint control 1 */ |
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#define USB0_ENDPTCTRL1 MMIO32(USB0_BASE + 0x1C4) |
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#define USB0_ENDPTCTRL1 USB0_ENDPTCTRL(1) |
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/* Endpoint control 2 */ |
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#define USB0_ENDPTCTRL2 MMIO32(USB0_BASE + 0x1C8) |
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#define USB0_ENDPTCTRL2 USB0_ENDPTCTRL(2) |
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/* Endpoint control 3 */ |
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#define USB0_ENDPTCTRL3 MMIO32(USB0_BASE + 0x1CC) |
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#define USB0_ENDPTCTRL3 USB0_ENDPTCTRL(3) |
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/* Endpoint control 4 */ |
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#define USB0_ENDPTCTRL4 MMIO32(USB0_BASE + 0x1D0) |
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#define USB0_ENDPTCTRL4 USB0_ENDPTCTRL(4) |
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/* Endpoint control 5 */ |
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#define USB0_ENDPTCTRL5 MMIO32(USB0_BASE + 0x1D4) |
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#define USB0_ENDPTCTRL5 USB0_ENDPTCTRL(5) |
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/* --- USB0_CAPLENGTH values ------------------------------------ */ |
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/* CAPLENGTH: Indicates offset to add to the register base address at the beginning of the Operational Register */ |
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