mcu
/
libopencm3
mirror of https://github.com/libopencm3/libopencm3.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
Browse Source

csv contributions from GNU Radio Conference 2012 HackFest. Thanks, David!

pull/174/head
Michael Ossmann 12 years ago
committed by Piotr Esden-Tempski
parent
df2ac8bbac
commit
299806bc4e
5 changed files with 290 additions and 0 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Split View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 2
      scripts/data/lpc43xx/README
  2. 77
      scripts/data/lpc43xx/adc.csv
  3. 58
      scripts/data/lpc43xx/i2c.csv
  4. 90
      scripts/data/lpc43xx/i2s.csv
  5. 63
      scripts/data/lpc43xx/ssp.csv

2
scripts/data/lpc43xx/README
View File

@ -19,3 +19,5 @@ The access field may consist of any of the following codes:
rws: read/write one to set
w: write only
ws: write one to set
Descriptions containing commas are quoted.

77
scripts/data/lpc43xx/adc.csv
View File

@ -0,0 +1,77 @@
ADC0_CR,0,8,SEL,Selects which of the ADCn_[7:0] inputs are to be sampled and converted,0,rw
ADC0_CR,8,8,CLKDIV,The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter,0,rw
ADC0_CR,16,1,BURST,Controls Burst mode,0,rw
ADC0_CR,17,3,CLKS,"This field selects the number of clocks used for each conversion in Burst mode and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).",0,rw
ADC0_CR,21,1,PDN,Power mode,0,rw
ADC0_CR,24,3,START,Controls the start of an A/D conversion when the BURST bit is 0,0,rw
ADC0_CR,27,1,EDGE,Controls rising or falling edge on the selected signal for the start of a conversion,0,rw
ADC1_CR,0,8,SEL,Selects which of the ADCn_[7:0] inputs are to be sampled and converted,0,rw
ADC1_CR,8,8,CLKDIV,The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter,0,rw
ADC1_CR,16,1,BURST,Controls Burst mode,0,rw
ADC1_CR,17,3,CLKS,"This field selects the number of clocks used for each conversion in Burst mode and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).",0,rw
ADC1_CR,21,1,PDN,Power mode,0,rw
ADC1_CR,24,3,START,Controls the start of an A/D conversion when the BURST bit is 0,0,rw
ADC1_CR,27,1,EDGE,Controls rising or falling edge on the selected signal for the start of a conversion,0,rw
ADC0_GDR,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin",0,r
ADC0_GDR,24,3,CHN,These bits contain the channel from which the LS bits were converted,0,r
ADC0_GDR,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits,0,r
ADC0_GDR,31,1,DONE,This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written,0,r
ADC1_GDR,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin",0,r
ADC1_GDR,24,3,CHN,These bits contain the channel from which the LS bits were converted,0,r
ADC1_GDR,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits,0,r
ADC1_GDR,31,1,DONE,This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written,0,r
ADC0_INTEN,0,8,ADINTEN,These bits allow control over which A/D channels generate interrupts for conversion completion,0,rw
ADC0_INTEN,8,1,ADGINTEN,"When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts.",1,rw
ADC1_INTEN,0,8,ADINTEN,These bits allow control over which A/D channels generate interrupts for conversion completion,0,rw
ADC1_INTEN,8,1,ADGINTEN,"When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts.",1,rw
ADC0_DR0,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC0 pin divided by the reference voltage on the VDDA pin",0,r
ADC0_DR0,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC0_DR0,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC1_DR0,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC0 pin divided by the reference voltage on the VDDA pin",0,r
ADC1_DR0,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC1_DR0,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC0_DR1,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC1 pin divided by the reference voltage on the VDDA pin",0,r
ADC0_DR1,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC0_DR1,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC1_DR1,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC1 pin divided by the reference voltage on the VDDA pin",0,r
ADC1_DR1,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC1_DR1,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC0_DR2,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC2 pin divided by the reference voltage on the VDDA pin",0,r
ADC0_DR2,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC0_DR2,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC1_DR2,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC2 pin divided by the reference voltage on the VDDA pin",0,r
ADC1_DR2,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC1_DR2,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC0_DR3,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC3 pin divided by the reference voltage on the VDDA pin",0,r
ADC0_DR3,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC0_DR3,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC1_DR3,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC3 pin divided by the reference voltage on the VDDA pin",0,r
ADC1_DR3,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC1_DR3,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC0_DR4,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC4 pin divided by the reference voltage on the VDDA pin",0,r
ADC0_DR4,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC0_DR4,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC1_DR4,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC4 pin divided by the reference voltage on the VDDA pin",0,r
ADC1_DR4,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC1_DR4,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC0_DR5,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC5 pin divided by the reference voltage on the VDDA pin",0,r
ADC0_DR5,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC0_DR5,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC1_DR5,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC5 pin divided by the reference voltage on the VDDA pin",0,r
ADC1_DR5,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC1_DR5,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC0_DR6,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC6 pin divided by the reference voltage on the VDDA pin",0,r
ADC0_DR6,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC0_DR6,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC1_DR6,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC6 pin divided by the reference voltage on the VDDA pin",0,r
ADC1_DR6,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC1_DR6,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC0_DR7,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC7 pin divided by the reference voltage on the VDDA pin",0,r
ADC0_DR7,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC0_DR7,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC1_DR7,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC7 pin divided by the reference voltage on the VDDA pin",0,r
ADC1_DR7,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC1_DR7,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC0_STAT,0,8,DONE,These bits mirror the DONE status flags that appear in the result register for each A/D channel.,0,r
ADC0_STAT,8,8,OVERRUN,These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel.,0,r
ADC0_STAT,16,1,ADINT,This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register.,0,r
Can't render this file because it has a wrong number of fields in line 18.

58
scripts/data/lpc43xx/i2c.csv
View File

@ -0,0 +1,58 @@
I2C0_CONSET,2,1,AA,Assert acknowledge flag,0,rw
I2C0_CONSET,3,1,SI,I2C interrupt flag,0,rw
I2C0_CONSET,4,1,STO,STOP flag,0,rw
I2C0_CONSET,5,1,STA,START flag,0,rw
I2C0_CONSET,6,1,I2EN,I2C interface enable,0,rw
I2C1_CONSET,2,1,AA,Assert acknowledge flag,0,rw
I2C1_CONSET,3,1,SI,I2C interrupt flag,0,rw
I2C1_CONSET,4,1,STO,STOP flag,0,rw
I2C1_CONSET,5,1,STA,START flag,0,rw
I2C1_CONSET,6,1,I2EN,I2C interface enable,0,rw
I2C0_STAT,3,5,STATUS,These bits give the actual status information about the I2C interface,0x1f,r
I2C1_STAT,3,5,STATUS,These bits give the actual status information about the I2C interface,0x1f,r
I2C0_DAT,0,8,DATA,This register holds data values that have been received or are to be transmitted,0,rw
I2C1_DAT,0,8,DATA,This register holds data values that have been received or are to be transmitted,0,rw
I2C0_ADR0,0,1,GC,General Call enable bit,0,rw
I2C0_ADR0,1,7,ADDRESS,The I2C device address for slave mode,0,rw
I2C1_ADR0,0,1,GC,General Call enable bit,0,rw
I2C1_ADR0,1,7,ADDRESS,The I2C device address for slave mode,0,rw
I2C0_SCLH,0,16,SCLH,Count for SCL HIGH time period selection,0x0004,rw
I2C1_SCLH,0,16,SCLH,Count for SCL HIGH time period selection,0x0004,rw
I2C0_SCLL,0,16,SCLL,Count for SCL LOW time period selection,0x0004,rw
I2C1_SCLL,0,16,SCLL,Count for SCL LOW time period selection,0x0004,rw
I2C0_CONCLR,2,1,AAC,Assert acknowledge Clear bit,0,w
I2C0_CONCLR,3,1,SIC,I2C interrupt Clear bit,0,w
I2C0_CONCLR,5,1,STAC,START flag Clear bit,0,w
I2C0_CONCLR,6,1,I2ENC,I2C interface Disable bit,0,w
I2C1_CONCLR,2,1,AAC,Assert acknowledge Clear bit,0,w
I2C1_CONCLR,3,1,SIC,I2C interrupt Clear bit,0,w
I2C1_CONCLR,5,1,STAC,START flag Clear bit,0,w
I2C1_CONCLR,6,1,I2ENC,I2C interface Disable bit,0,w
I2C0_MMCTRL,0,1,MM_ENA,Monitor mode enable,0,rw
I2C0_MMCTRL,1,1,ENA_SCL,SCL output enable,0,rw
I2C0_MMCTRL,2,1,MATCH_ALL,Select interrupt register match,0,rw
I2C1_MMCTRL,0,1,MM_ENA,Monitor mode enable,0,rw
I2C1_MMCTRL,1,1,ENA_SCL,SCL output enable,0,rw
I2C1_MMCTRL,2,1,MATCH_ALL,Select interrupt register match,0,rw
I2C0_ADR1,0,1,GC,General Call enable bit,0,rw
I2C0_ADR1,1,7,ADDRESS,The I2C device address for slave mode,0,rw
I2C1_ADR1,0,1,GC,General Call enable bit,0,rw
I2C1_ADR1,1,7,ADDRESS,The I2C device address for slave mode,0,rw
I2C0_ADR2,0,1,GC,General Call enable bit,0,rw
I2C0_ADR2,1,7,ADDRESS,The I2C device address for slave mode,0,rw
I2C1_ADR2,0,1,GC,General Call enable bit,0,rw
I2C1_ADR2,1,7,ADDRESS,The I2C device address for slave mode,0,rw
I2C0_ADR3,0,1,GC,General Call enable bit,0,rw
I2C0_ADR3,1,7,ADDRESS,The I2C device address for slave mode,0,rw
I2C1_ADR3,0,1,GC,General Call enable bit,0,rw
I2C1_ADR3,1,7,ADDRESS,The I2C device address for slave mode,0,rw
I2C0_DATA_BUFFER,0,8,DATA,This register holds contents of the 8 MSBs of the DAT shift register,0,r
I2C1_DATA_BUFFER,0,8,DATA,This register holds contents of the 8 MSBs of the DAT shift register,0,r
I2C0_MASK0,1,7,MASK,Mask bits,0,rw
I2C1_MASK0,1,7,MASK,Mask bits,0,rw
I2C0_MASK1,1,7,MASK,Mask bits,0,rw
I2C1_MASK1,1,7,MASK,Mask bits,0,rw
I2C0_MASK2,1,7,MASK,Mask bits,0,rw
I2C1_MASK2,1,7,MASK,Mask bits,0,rw
I2C0_MASK3,1,7,MASK,Mask bits,0,rw
I2C1_MASK3,1,7,MASK,Mask bits,0,rw
Can't render this file because it has a wrong number of fields in line 36.

90
scripts/data/lpc43xx/i2s.csv
View File

@ -0,0 +1,90 @@
I2S0_DAO,0,2,WORDWIDTH,Selects the number of bytes in data,1,rw
I2S0_DAO,2,1,MONO,"When 1, data is of monaural format. When 0, the data is in stereo format",0,rw
I2S0_DAO,3,1,STOP,"When 1, disables accesses on FIFOs, places the transmit channel in mute mode",0,rw
I2S0_DAO,4,1,RESET,"When 1, asynchronously resets the transmit channel and FIFO",0,rw
I2S0_DAO,5,1,WS_SEL,"When 0, the interface is in master mode. When 1, the interface is in slave mode",1,rw
I2S0_DAO,6,9,WS_HALFPERIOD,"Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.",0x1f,rw
I2S0_DAO,15,1,MUTE,"When 1, the transmit channel sends only zeroes",1,rw
I2S1_DAO,0,2,WORDWIDTH,Selects the number of bytes in data,1,rw
I2S1_DAO,2,1,MONO,"When 1, data is of monaural format. When 0, the data is in stereo format",0,rw
I2S1_DAO,3,1,STOP,"When 1, disables accesses on FIFOs, places the transmit channel in mute mode",0,rw
I2S1_DAO,4,1,RESET,"When 1, asynchronously resets the transmit channel and FIFO",0,rw
I2S1_DAO,5,1,WS_SEL,"When 0, the interface is in master mode. When 1, the interface is in slave mode",1,rw
I2S1_DAO,6,9,WS_HALFPERIOD,"Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.",0x1f,rw
I2S1_DAO,15,1,MUTE,"When 1, the transmit channel sends only zeroes",1,rw
I2S0_DAI,0,2,WORDWIDTH,Selects the number of bytes in data,1,rw
I2S0_DAI,2,1,MONO,"When 1, data is of monaural format. When 0, the data is in stereo format",0,rw
I2S0_DAI,3,1,STOP,"When 1, disables accesses on FIFOs, places the transmit channel in mute mode",0,rw
I2S0_DAI,4,1,RESET,"When 1, asynchronously resets the transmit channel and FIFO",0,rw
I2S0_DAI,5,1,WS_SEL,"When 0, the interface is in master mode. When 1, the interface is in slave mode",1,rw
I2S0_DAI,6,9,WS_HALFPERIOD,"Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.",0x1f,rw
I2S0_DAI,15,1,MUTE,"When 1, the transmit channel sends only zeroes",1,rw
I2S1_DAI,0,2,WORDWIDTH,Selects the number of bytes in data,1,rw
I2S1_DAI,2,1,MONO,"When 1, data is of monaural format. When 0, the data is in stereo format",0,rw
I2S1_DAI,3,1,STOP,"When 1, disables accesses on FIFOs, places the transmit channel in mute mode",0,rw
I2S1_DAI,4,1,RESET,"When 1, asynchronously resets the transmit channel and FIFO",0,rw
I2S1_DAI,5,1,WS_SEL,"When 0, the interface is in master mode. When 1, the interface is in slave mode",1,rw
I2S1_DAI,6,9,WS_HALFPERIOD,"Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.",0x1f,rw
I2S1_DAI,15,1,MUTE,"When 1, the transmit channel sends only zeroes",1,rw
I2S0_TXFIFO,0,32,I2STXFIFO,8 x 32-bit transmit FIFO,0,w
I2S1_TXFIFO,0,32,I2STXFIFO,8 x 32-bit transmit FIFO,0,w
I2S0_RXFIFO,0,32,I2SRXFIFO,8 x 32-bit receive FIFO,0,r
I2S1_RXFIFO,0,32,I2SRXFIFO,8 x 32-bit receive FIFO,0,r
I2S0_STATE,0,1,IRQ,This bit reflects the presence of Receive Interrupt or Transmit Interrupt,1,r
I2S0_STATE,1,1,DMAREQ1,This bit reflects the presence of Receive or Transmit DMA Request 1,1,r
I2S0_STATE,2,1,DMAREQ2,This bit reflects the presence of Receive or Transmit DMA Request 2,1,r
I2S0_STATE,8,4,RX_LEVEL,Reflects the current level of the Receive FIFO,0,r
I2S0_STATE,16,4,TX_LEVEL,Reflects the current level of the Transmit FIFO,0,r
I2S1_STATE,0,1,IRQ,This bit reflects the presence of Receive Interrupt or Transmit Interrupt,1,r
I2S1_STATE,1,1,DMAREQ1,This bit reflects the presence of Receive or Transmit DMA Request 1,1,r
I2S1_STATE,2,1,DMAREQ2,This bit reflects the presence of Receive or Transmit DMA Request 2,1,r
I2S1_STATE,8,4,RX_LEVEL,Reflects the current level of the Receive FIFO,0,r
I2S1_STATE,16,4,TX_LEVEL,Reflects the current level of the Transmit FIFO,0,r
I2S0_DMA1,0,1,RX_DMA1_ENABLE,"When 1, enables DMA1 for I2S receive",0,rw
I2S0_DMA1,1,1,TX_DMA1_ENABLE,"When 1, enables DMA1 for I2S transmit",0,rw
I2S0_DMA1,8,4,RX_DEPTH_DMA1,Set the FIFO level that triggers a receive DMA request on DMA1,0,rw
I2S0_DMA1,16,4,TX_DEPTH_DMA1,Set the FIFO level that triggers a transmit DMA request on DMA1,0,rw
I2S1_DMA1,0,1,RX_DMA1_ENABLE,"When 1, enables DMA1 for I2S receive",0,rw
I2S1_DMA1,1,1,TX_DMA1_ENABLE,"When 1, enables DMA1 for I2S transmit",0,rw
I2S1_DMA1,8,4,RX_DEPTH_DMA1,Set the FIFO level that triggers a receive DMA request on DMA1,0,rw
I2S1_DMA1,16,4,TX_DEPTH_DMA1,Set the FIFO level that triggers a transmit DMA request on DMA1,0,rw
I2S0_DMA2,0,1,RX_DMA2_ENABLE,"When 1, enables DMA2 for I2S receive",0,rw
I2S0_DMA2,1,1,TX_DMA2_ENABLE,"When 1, enables DMA2 for I2S transmit",0,rw
I2S0_DMA2,8,4,RX_DEPTH_DMA2,Set the FIFO level that triggers a receive DMA request on DMA2,0,rw
I2S0_DMA2,16,4,TX_DEPTH_DMA2,Set the FIFO level that triggers a transmit DMA request on DMA2,0,rw
I2S1_DMA2,0,1,RX_DMA2_ENABLE,"When 1, enables DMA2 for I2S receive",0,rw
I2S1_DMA2,1,1,TX_DMA2_ENABLE,"When 1, enables DMA2 for I2S transmit",0,rw
I2S1_DMA2,8,4,RX_DEPTH_DMA2,Set the FIFO level that triggers a receive DMA request on DMA2,0,rw
I2S1_DMA2,16,4,TX_DEPTH_DMA2,Set the FIFO level that triggers a transmit DMA request on DMA2,0,rw
I2S0_IRQ,0,1,RX_IRQ_ENABLE,"When 1, enables I2S receive interrupt",0,rw
I2S0_IRQ,1,1,TX_IRQ_ENABLE,"When 1, enables I2S transmit interrupt",0,rw
I2S0_IRQ,8,4,RX_DEPTH_IRQ,Set the FIFO level on which to create an irq request.,0,rw
I2S0_IRQ,16,4,TX_DEPTH_IRQ,Set the FIFO level on which to create an irq request.,0,rw
I2S1_IRQ,0,1,RX_IRQ_ENABLE,"When 1, enables I2S receive interrupt",0,rw
I2S1_IRQ,1,1,TX_IRQ_ENABLE,"When 1, enables I2S transmit interrupt",0,rw
I2S1_IRQ,8,4,RX_DEPTH_IRQ,Set the FIFO level on which to create an irq request.,0,rw
I2S1_IRQ,16,4,TX_DEPTH_IRQ,Set the FIFO level on which to create an irq request.,0,rw
I2S0_TXRATE,0,8,Y_DIVIDER,I2S transmit MCLK rate denominator,0,rw
I2S0_TXRATE,8,8,X_DIVIDER,I2S transmit MCLK rate numerator,0,rw
I2S1_TXRATE,0,8,Y_DIVIDER,I2S transmit MCLK rate denominator,0,rw
I2S1_TXRATE,8,8,X_DIVIDER,I2S transmit MCLK rate numerator,0,rw
I2S0_RXRATE,0,8,Y_DIVIDER,I2S receive MCLK rate denominator,0,rw
I2S0_RXRATE,8,8,X_DIVIDER,I2S receive MCLK rate numerator,0,rw
I2S1_RXRATE,0,8,Y_DIVIDER,I2S receive MCLK rate denominator,0,rw
I2S1_RXRATE,8,8,X_DIVIDER,I2S receive MCLK rate numerator,0,rw
I2S0_TXBITRATE,0,6,TX_BITRATE,I2S transmit bit rate,0,rw
I2S1_TXBITRATE,0,6,TX_BITRATE,I2S transmit bit rate,0,rw
I2S0_RXBITRATE,0,6,RX_BITRATE,I2S receive bit rate,0,rw
I2S1_RXBITRATE,0,6,RX_BITRATE,I2S receive bit rate,0,rw
I2S0_TXMODE,0,2,TXCLKSEL,Clock source selection for the transmit bit clock divider,0,rw
I2S0_TXMODE,2,1,TX4PIN,Transmit 4-pin mode selection,0,rw
I2S0_TXMODE,3,1,TXMCENA,Enable for the TX_MCLK output,0,rw
I2S1_TXMODE,0,2,TXCLKSEL,Clock source selection for the transmit bit clock divider,0,rw
I2S1_TXMODE,2,1,TX4PIN,Transmit 4-pin mode selection,0,rw
I2S1_TXMODE,3,1,TXMCENA,Enable for the TX_MCLK output,0,rw
I2S0_RXMODE,0,2,RXCLKSEL,Clock source selection for the receive bit clock divider,0,rw
I2S0_RXMODE,2,1,RX4PIN,Receive 4-pin mode selection,0,rw
I2S0_RXMODE,3,1,RXMCENA,Enable for the RX_MCLK output,0,rw
I2S1_RXMODE,0,2,RXCLKSEL,Clock source selection for the receive bit clock divider,0,rw
I2S1_RXMODE,2,1,RX4PIN,Receive 4-pin mode selection,0,rw
I2S1_RXMODE,3,1,RXMCENA,Enable for the RX_MCLK output,0,rw
Can't render this file because it contains an unexpected character in line 24 and column 0.

63
scripts/data/lpc43xx/ssp.csv
View File

@ -0,0 +1,63 @@
SSP0_CR0,0,4,DSS,Data Size Select,0,rw
SSP0_CR0,4,2,FRF,Frame Format,0,rw
SSP0_CR0,6,1,CPOL,Clock Out Polarity,0,rw
SSP0_CR0,7,1,CPHA,Clock Out Phase,0,rw
SSP0_CR0,8,8,SCR,Serial Clock Rate,0,rw
SSP1_CR0,0,4,DSS,Data Size Select,0,rw
SSP1_CR0,4,2,FRF,Frame Format,0,rw
SSP1_CR0,6,1,CPOL,Clock Out Polarity,0,rw
SSP1_CR0,7,1,CPHA,Clock Out Phase,0,rw
SSP1_CR0,8,8,SCR,Serial Clock Rate,0,rw
SSP0_CR1,0,1,LBM,Loop Back Mode,0,rw
SSP0_CR1,1,1,SSE,SSP Enable,0,rw
SSP0_CR1,2,1,MS,Master/Slave Mode,0,rw
SSP0_CR1,3,1,SOD,Slave Output Disable,0,rw
SSP1_CR1,1,1,SSE,SSP Enable,0,rw
SSP1_CR1,2,1,MS,Master/Slave Mode,0,rw
SSP1_CR1,3,1,SOD,Slave Output Disable,0,rw
SSP0_DR,0,16,DATA,"Software can write data to be transmitted to this register, and read data that has been",0,rw
SSP1_DR,0,16,DATA,"Software can write data to be transmitted to this register, and read data that has been",0,rw
SSP0_SR,0,1,TFE,Transmit FIFO Empty,1,r
SSP0_SR,1,1,TNF,Transmit FIFO Not Full,1,r
SSP0_SR,2,1,RNE,Receive FIFO Not Empty,0,r
SSP0_SR,3,1,RFF,Receive FIFO Full,0,r
SSP0_SR,4,1,BSY,Busy.,0,r
SSP1_SR,0,1,TFE,Transmit FIFO Empty,1,r
SSP1_SR,1,1,TNF,Transmit FIFO Not Full,1,r
SSP1_SR,2,1,RNE,Receive FIFO Not Empty,0,r
SSP1_SR,3,1,RFF,Receive FIFO Full,0,r
SSP1_SR,4,1,BSY,Busy.,0,r
SSP0_CPSR,0,8,CPSDVSR,SSP Clock Prescale Register,0,rw
SSP1_CPSR,0,8,CPSDVSR,SSP Clock Prescale Register,0,rw
SSP0_IMSC,0,1,RORIM,Software should set this bit to enable interrupt when a Receive Overrun occurs,0,rw
SSP0_IMSC,1,1,RTIM,Software should set this bit to enable interrupt when a Receive Time-out condition occurs,0,rw
SSP0_IMSC,2,1,RXIM,Software should set this bit to enable interrupt when the Rx FIFO is at least half full,0,rw
SSP0_IMSC,3,1,TXIM,Software should set this bit to enable interrupt when the Tx FIFO is at least half empty,0,rw
SSP1_IMSC,0,1,RORIM,Software should set this bit to enable interrupt when a Receive Overrun occurs,0,rw
SSP1_IMSC,1,1,RTIM,Software should set this bit to enable interrupt when a Receive Time-out condition occurs,0,rw
SSP1_IMSC,2,1,RXIM,Software should set this bit to enable interrupt when the Rx FIFO is at least half full,0,rw
SSP1_IMSC,3,1,TXIM,Software should set this bit to enable interrupt when the Tx FIFO is at least half empty,0,rw
SSP0_RIS,0,1,RORRIS,This bit is 1 if another frame was completely received while the RxFIFO was full,0,r
SSP0_RIS,1,1,RTRIS,"This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period",0,r
SSP0_RIS,2,1,RXRIS,This bit is 1 if the Rx FIFO is at least half full,0,r
SSP0_RIS,3,1,TXRIS,This bit is 1 if the Tx FIFO is at least half empty,1,r
SSP1_RIS,0,1,RORRIS,This bit is 1 if another frame was completely received while the RxFIFO was full,0,r
SSP1_RIS,1,1,RTRIS,"This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period",0,r
SSP1_RIS,2,1,RXRIS,This bit is 1 if the Rx FIFO is at least half full,0,r
SSP1_RIS,3,1,TXRIS,This bit is 1 if the Tx FIFO is at least half empty,1,r
SSP0_MIS,0,1,RORMIS,"This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled",0,r
SSP0_MIS,1,1,RTMIS,"This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled",0,r
SSP0_MIS,2,1,RXMIS,"This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled",0,r
SSP0_MIS,3,1,TXMIS,"This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled",0,r
SSP1_MIS,0,1,RORMIS,"This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled",0,r
SSP1_MIS,1,1,RTMIS,"This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled",0,r
SSP1_MIS,2,1,RXMIS,"This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled",0,r
SSP1_MIS,3,1,TXMIS,"This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled",0,r
SSP0_ICR,0,1,RORIC,Writing a 1 to this bit clears the 'frame was received when RxFIFO was full' interrupt,,w
SSP0_ICR,1,1,RTIC,Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt,,w
SSP1_ICR,0,1,RORIC,Writing a 1 to this bit clears the 'frame was received when RxFIFO was full' interrupt,,w
SSP1_ICR,1,1,RTIC,Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt,,w
SSP0_DMACR,0,1,RXDMAE,Receive DMA Enable,0,rw
SSP0_DMACR,1,1,TXDMAE,Transmit DMA Enable,0,rw
SSP1_DMACR,0,1,RXDMAE,Receive DMA Enable,0,rw
SSP1_DMACR,1,1,TXDMAE,Transmit DMA Enable,0,rw
Can't render this file because it has a wrong number of fields in line 37.
Write Preview
Loading…
Cancel
Save