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stm32g0: rcc: add missing periphs 

A bunch of periphs on newer parts weren't defined.  Add their
enable/reset bit definitions so they can be used.

Signed-off-by: Karl Palsson <karlp@tweak.au>
pull/1461/head
Karl Palsson 2 years ago
parent
5796f41caa
commit
2c180d8431
1 changed files with 56 additions and 9 deletions
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  1. 65
      include/libopencm3/stm32/g0/rcc.h

65
include/libopencm3/stm32/g0/rcc.h
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@ -305,7 +305,9 @@
#define RCC_AHBRSTR_AESRST (1 << 16)
#define RCC_AHBRSTR_CRCRST (1 << 12)
#define RCC_AHBRSTR_FLASHRST (1 << 8)
#define RCC_AHBRSTR_DMARST (1 << 0)
#define RCC_AHBRSTR_DMA2RST (1 << 1)
#define RCC_AHBRSTR_DMA1RST (1 << 0)
#define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMA1RST
/**@}*/
/** @defgroup rcc_apb1rstr_rst RCC_APBRSTRx reset values (full set)
@ -319,15 +321,25 @@
#define RCC_APBRSTR1_DBGRST (1 << 27)
#define RCC_APBRSTR1_UCPD2RST (1 << 26)
#define RCC_APBRSTR1_UCPD1RST (1 << 25)
#define RCC_APBRSTR1_CECRST (1 << 24)
#define RCC_APBRSTR1_I2C3RST (1 << 23)
#define RCC_APBRSTR1_I2C2RST (1 << 22)
#define RCC_APBRSTR1_I2C1RST (1 << 21)
#define RCC_APBRSTR1_LPUART1RST (1 << 20)
#define RCC_APBRSTR1_USART4RST (1 << 19)
#define RCC_APBRSTR1_USART3RST (1 << 18)
#define RCC_APBRSTR1_USART2RST (1 << 17)
#define RCC_APBRSTR1_CRSRST (1 << 16)
#define RCC_APBRSTR1_SPI3RST (1 << 15)
#define RCC_APBRSTR1_SPI2RST (1 << 14)
#define RCC_APBRSTR1_USBRST (1 << 13)
#define RCC_APBRSTR1_FDCANRST (1 << 12)
#define RCC_APBRSTR1_USART6RST (1 << 9)
#define RCC_APBRSTR1_USART5RST (1 << 8)
#define RCC_APBRSTR1_LPUART2RST (1 << 7)
#define RCC_APBRSTR1_TIM7RST (1 << 5)
#define RCC_APBRSTR1_TIM6RST (1 << 4)
#define RCC_APBRSTR1_TIM4RST (1 << 2)
#define RCC_APBRSTR1_TIM3RST (1 << 1)
#define RCC_APBRSTR1_TIM2RST (1 << 0)
/**@}*/
@ -337,7 +349,6 @@
#define RCC_APBRSTR2_ADCRST (1 << 20)
#define RCC_APBRSTR2_TIM17RST (1 << 18)
#define RCC_APBRSTR2_TIM16RST (1 << 17)
#define RCC_APBRSTR2_TIM16RST (1 << 17)
#define RCC_APBRSTR2_TIM15RST (1 << 16)
#define RCC_APBRSTR2_TIM14RST (1 << 15)
#define RCC_APBRSTR2_USART1RST (1 << 14)
@ -353,7 +364,9 @@
#define RCC_AHBENR_AESEN (1 << 16)
#define RCC_AHBENR_CRCEN (1 << 12)
#define RCC_AHBENR_FLASHEN (1 << 8)
#define RCC_AHBENR_DMAEN (1 << 0)
#define RCC_AHBENR_DMA2EN (1 << 1)
#define RCC_AHBENR_DMA1EN (1 << 0)
#define RCC_AHBENR_DMAEN RCC_AHBENR_DMA1EN
/**@}*/
/** @defgroup rcc_apb1enr_en RCC_APBENRx enable values (full set)
@ -652,8 +665,9 @@ enum rcc_periph_clken {
RCC_AES = _REG_BIT(RCC_AHBENR_OFFSET, 16),
RCC_CRC = _REG_BIT(RCC_AHBENR_OFFSET, 12),
RCC_FLASH = _REG_BIT(RCC_AHBENR_OFFSET, 8),
RCC_DMA = _REG_BIT(RCC_AHBENR_OFFSET, 0),
RCC_DMA1 = _REG_BIT(RCC_AHBENR_OFFSET, 0), /* Compatibility */
RCC_DMA2 = _REG_BIT(RCC_AHBENR_OFFSET, 1),
RCC_DMA1 = _REG_BIT(RCC_AHBENR_OFFSET, 0),
RCC_DMA = _REG_BIT(RCC_AHBENR_OFFSET, 0), /* Compatibility */
RCC_LPTIM1 = _REG_BIT(RCC_APBENR1_OFFSET, 31),
RCC_LPTIM2 = _REG_BIT(RCC_APBENR1_OFFSET, 30),
@ -663,15 +677,26 @@ enum rcc_periph_clken {
RCC_UCPD2 = _REG_BIT(RCC_APBENR1_OFFSET, 26),
RCC_UCPD1 = _REG_BIT(RCC_APBENR1_OFFSET, 25),
RCC_CEC = _REG_BIT(RCC_APBENR1_OFFSET, 24),
RCC_I2C3 = _REG_BIT(RCC_APBENR1_OFFSET, 23),
RCC_I2C2 = _REG_BIT(RCC_APBENR1_OFFSET, 22),
RCC_I2C1 = _REG_BIT(RCC_APBENR1_OFFSET, 21),
RCC_LPUART1 = _REG_BIT(RCC_APBENR1_OFFSET, 20),
RCC_USART4 = _REG_BIT(RCC_APBENR1_OFFSET, 19),
RCC_USART3 = _REG_BIT(RCC_APBENR1_OFFSET, 18),
RCC_USART2 = _REG_BIT(RCC_APBENR1_OFFSET, 17),
RCC_CRS = _REG_BIT(RCC_APBENR1_OFFSET, 16),
RCC_SPI3 = _REG_BIT(RCC_APBENR1_OFFSET, 15),
RCC_SPI2 = _REG_BIT(RCC_APBENR1_OFFSET, 14),
RCC_USB = _REG_BIT(RCC_APBENR1_OFFSET, 13),
RCC_FDCAN = _REG_BIT(RCC_APBENR1_OFFSET, 12),
RCC_WWDG = _REG_BIT(RCC_APBENR1_OFFSET, 11),
RCC_RTCAPB = _REG_BIT(RCC_APBENR1_OFFSET, 10),
RCC_USART6 = _REG_BIT(RCC_APBENR1_OFFSET, 9),
RCC_USART5 = _REG_BIT(RCC_APBENR1_OFFSET, 8),
RCC_LPUART2 = _REG_BIT(RCC_APBENR1_OFFSET, 7),
RCC_TIM7 = _REG_BIT(RCC_APBENR1_OFFSET, 5),
RCC_TIM6 = _REG_BIT(RCC_APBENR1_OFFSET, 4),
RCC_TIM4 = _REG_BIT(RCC_APBENR1_OFFSET, 2),
RCC_TIM3 = _REG_BIT(RCC_APBENR1_OFFSET, 1),
RCC_TIM2 = _REG_BIT(RCC_APBENR1_OFFSET, 0),
@ -695,9 +720,11 @@ enum rcc_periph_clken {
SCC_RNG = _REG_BIT(RCC_AHBSMENR_OFFSET, 18),
SCC_AES = _REG_BIT(RCC_AHBSMENR_OFFSET, 16),
SCC_CRC = _REG_BIT(RCC_AHBSMENR_OFFSET, 12),
SCC_SRAM = _REG_BIT(RCC_AHBSMENR_OFFSET, 9),
SCC_FLASH = _REG_BIT(RCC_AHBSMENR_OFFSET, 8),
SCC_DMA = _REG_BIT(RCC_AHBSMENR_OFFSET, 0),
SCC_DMA1 = _REG_BIT(RCC_AHBSMENR_OFFSET, 0), /* Compatibility */
SCC_DMA2 = _REG_BIT(RCC_AHBSMENR_OFFSET, 1),
SCC_DMA1 = _REG_BIT(RCC_AHBSMENR_OFFSET, 0),
SCC_DMA = _REG_BIT(RCC_AHBSMENR_OFFSET, 0), /* Compatibility */
SCC_LPTIM1 = _REG_BIT(RCC_APBSMENR1_OFFSET, 31),
SCC_LPTIM2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 30),
@ -707,13 +734,23 @@ enum rcc_periph_clken {
SCC_UCPD2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 26),
SCC_UCPD1 = _REG_BIT(RCC_APBSMENR1_OFFSET, 25),
SCC_CEC = _REG_BIT(RCC_APBSMENR1_OFFSET, 24),
SCC_I2C3 = _REG_BIT(RCC_APBSMENR1_OFFSET, 23),
SCC_I2C2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 22),
SCC_I2C1 = _REG_BIT(RCC_APBSMENR1_OFFSET, 21),
SCC_LPUART1 = _REG_BIT(RCC_APBSMENR1_OFFSET, 20),
SCC_USART4 = _REG_BIT(RCC_APBSMENR1_OFFSET, 19),
SCC_USART3 = _REG_BIT(RCC_APBSMENR1_OFFSET, 18),
SCC_USART2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 17),
SCC_CRS = _REG_BIT(RCC_APBSMENR1_OFFSET, 16),
SCC_SPI3 = _REG_BIT(RCC_APBSMENR1_OFFSET, 15),
SCC_SPI2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 14),
SCC_USB = _REG_BIT(RCC_APBSMENR1_OFFSET, 13),
SCC_FDCAN = _REG_BIT(RCC_APBSMENR1_OFFSET, 12),
SCC_WWDG = _REG_BIT(RCC_APBSMENR1_OFFSET, 11),
SCC_RTCAPB = _REG_BIT(RCC_APBSMENR1_OFFSET, 10),
SCC_USART6 = _REG_BIT(RCC_APBSMENR1_OFFSET, 9),
SCC_USART5 = _REG_BIT(RCC_APBSMENR1_OFFSET, 8),
SCC_LPUART2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 7),
SCC_TIM7 = _REG_BIT(RCC_APBSMENR1_OFFSET, 5),
SCC_TIM6 = _REG_BIT(RCC_APBSMENR1_OFFSET, 4),
SCC_TIM3 = _REG_BIT(RCC_APBSMENR1_OFFSET, 1),
@ -742,8 +779,9 @@ enum rcc_periph_rst {
RST_AES = _REG_BIT(RCC_AHBRSTR_OFFSET, 16),
RST_CRC = _REG_BIT(RCC_AHBRSTR_OFFSET, 12),
RST_FLASH = _REG_BIT(RCC_AHBRSTR_OFFSET, 8),
RST_DMA = _REG_BIT(RCC_AHBRSTR_OFFSET, 0),
RST_DMA1 = _REG_BIT(RCC_AHBRSTR_OFFSET, 0), /* Compatibility */
RST_DMA2 = _REG_BIT(RCC_AHBRSTR_OFFSET, 1),
RST_DMA1 = _REG_BIT(RCC_AHBRSTR_OFFSET, 0),
RST_DMA = _REG_BIT(RCC_AHBRSTR_OFFSET, 0), /* Compatibility */
RST_LPTIM1 = _REG_BIT(RCC_APBRSTR1_OFFSET, 31),
RST_LPTIM2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 30),
@ -753,15 +791,24 @@ enum rcc_periph_rst {
RST_UCPD2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 26),
RST_UCPD1 = _REG_BIT(RCC_APBRSTR1_OFFSET, 25),
RST_CEC = _REG_BIT(RCC_APBRSTR1_OFFSET, 24),
RST_I2C3 = _REG_BIT(RCC_APBRSTR1_OFFSET, 23),
RST_I2C2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 22),
RST_I2C1 = _REG_BIT(RCC_APBRSTR1_OFFSET, 21),
RST_LPUART1 = _REG_BIT(RCC_APBRSTR1_OFFSET, 20),
RST_USART4 = _REG_BIT(RCC_APBRSTR1_OFFSET, 19),
RST_USART3 = _REG_BIT(RCC_APBRSTR1_OFFSET, 18),
RST_USART2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 17),
RST_CRS = _REG_BIT(RCC_APBRSTR1_OFFSET, 16),
RST_SPI3 = _REG_BIT(RCC_APBRSTR1_OFFSET, 15),
RST_SPI2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 14),
RST_USB = _REG_BIT(RCC_APBRSTR1_OFFSET, 13),
RST_FDCAN = _REG_BIT(RCC_APBRSTR1_OFFSET, 12),
RST_USART6 = _REG_BIT(RCC_APBRSTR1_OFFSET, 9),
RST_USART5 = _REG_BIT(RCC_APBRSTR1_OFFSET, 8),
RST_LPUART2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 7),
RST_TIM7 = _REG_BIT(RCC_APBRSTR1_OFFSET, 5),
RST_TIM6 = _REG_BIT(RCC_APBRSTR1_OFFSET, 4),
RST_TIM4 = _REG_BIT(RCC_APBRSTR1_OFFSET, 2),
RST_TIM3 = _REG_BIT(RCC_APBRSTR1_OFFSET, 1),
RST_TIM2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 0),

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