Michael Ossmann
13 years ago
1 changed files with 156 additions and 0 deletions
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/*
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* This file is part of the libopencm3 project. |
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* |
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* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com> |
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* |
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* This library is free software: you can redistribute it and/or modify |
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* it under the terms of the GNU Lesser General Public License as published by |
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* the Free Software Foundation, either version 3 of the License, or |
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* (at your option) any later version. |
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* |
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* This library is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU Lesser General Public License for more details. |
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* |
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* You should have received a copy of the GNU Lesser General Public License |
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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#ifndef LPC43XX_TIMER_H |
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#define LPC43XX_TIMER_H |
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#include <libopencm3/cm3/common.h> |
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#include <libopencm3/lpc43xx/memorymap.h> |
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/* --- Convenience macros -------------------------------------------------- */ |
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/* Timer base addresses */ |
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#define TIMER0 TIMER0_BASE |
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#define TIMER1 TIMER1_BASE |
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#define TIMER2 TIMER2_BASE |
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#define TIMER3 TIMER3_BASE |
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/* --- Timer registers ----------------------------------------------------- */ |
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/* Interrupt Register */ |
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#define TIMER_IR(timer) MMIO32(timer + 0x000) |
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#define TIMER0_IR TIMER_IR(TIMER0) |
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#define TIMER1_IR TIMER_IR(TIMER1) |
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#define TIMER2_IR TIMER_IR(TIMER2) |
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#define TIMER3_IR TIMER_IR(TIMER3) |
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/* Timer Control Register */ |
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#define TIMER_TCR(timer) MMIO32(timer + 0x004) |
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#define TIMER0_TCR TIMER_TCR(TIMER0) |
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#define TIMER1_TCR TIMER_TCR(TIMER1) |
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#define TIMER2_TCR TIMER_TCR(TIMER2) |
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#define TIMER3_TCR TIMER_TCR(TIMER3) |
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/* Timer Counter */ |
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#define TIMER_TC(timer) MMIO32(timer + 0x008) |
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#define TIMER0_TC TIMER_TC(TIMER0) |
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#define TIMER1_TC TIMER_TC(TIMER1) |
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#define TIMER2_TC TIMER_TC(TIMER2) |
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#define TIMER3_TC TIMER_TC(TIMER3) |
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/* Prescale Register */ |
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#define TIMER_PR(timer) MMIO32(timer + 0x00C) |
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#define TIMER0_PR TIMER_PR(TIMER0) |
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#define TIMER1_PR TIMER_PR(TIMER1) |
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#define TIMER2_PR TIMER_PR(TIMER2) |
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#define TIMER3_PR TIMER_PR(TIMER3) |
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/* Prescale Counter */ |
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#define TIMER_PC(timer) MMIO32(timer + 0x010) |
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#define TIMER0_PC TIMER_PC(TIMER0) |
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#define TIMER1_PC TIMER_PC(TIMER1) |
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#define TIMER2_PC TIMER_PC(TIMER2) |
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#define TIMER3_PC TIMER_PC(TIMER3) |
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/* Match Control Register */ |
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#define TIMER_MCR(timer) MMIO32(timer + 0x014) |
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#define TIMER0_MCR TIMER_MCR(TIMER0) |
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#define TIMER1_MCR TIMER_MCR(TIMER1) |
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#define TIMER2_MCR TIMER_MCR(TIMER2) |
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#define TIMER3_MCR TIMER_MCR(TIMER3) |
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/* Match Register 0 */ |
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#define TIMER_MR0(timer) MMIO32(timer + 0x018) |
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#define TIMER0_MR0 TIMER_MR0(TIMER0) |
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#define TIMER1_MR0 TIMER_MR0(TIMER1) |
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#define TIMER2_MR0 TIMER_MR0(TIMER2) |
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#define TIMER3_MR0 TIMER_MR0(TIMER3) |
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/* Match Register 1 */ |
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#define TIMER_MR1(timer) MMIO32(timer + 0x01C) |
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#define TIMER0_MR1 TIMER_MR1(TIMER0) |
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#define TIMER1_MR1 TIMER_MR1(TIMER1) |
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#define TIMER2_MR1 TIMER_MR1(TIMER2) |
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#define TIMER3_MR1 TIMER_MR1(TIMER3) |
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/* Match Register 2 */ |
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#define TIMER_MR2(timer) MMIO32(timer + 0x020) |
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#define TIMER0_MR2 TIMER_MR2(TIMER0) |
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#define TIMER1_MR2 TIMER_MR2(TIMER1) |
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#define TIMER2_MR2 TIMER_MR2(TIMER2) |
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#define TIMER3_MR2 TIMER_MR2(TIMER3) |
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/* Match Register 3 */ |
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#define TIMER_MR3(timer) MMIO32(timer + 0x024) |
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#define TIMER0_MR3 TIMER_MR3(TIMER0) |
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#define TIMER1_MR3 TIMER_MR3(TIMER1) |
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#define TIMER2_MR3 TIMER_MR3(TIMER2) |
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#define TIMER3_MR3 TIMER_MR3(TIMER3) |
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/* Capture Control Register */ |
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#define TIMER_CCR(timer) MMIO32(timer + 0x028) |
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#define TIMER0_CCR TIMER_CCR(TIMER0) |
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#define TIMER1_CCR TIMER_CCR(TIMER1) |
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#define TIMER2_CCR TIMER_CCR(TIMER2) |
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#define TIMER3_CCR TIMER_CCR(TIMER3) |
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/* Capture Register 0 */ |
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#define TIMER_CR0(timer) MMIO32(timer + 0x02C) |
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#define TIMER0_CR0 TIMER_CR0(TIMER0) |
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#define TIMER1_CR0 TIMER_CR0(TIMER1) |
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#define TIMER2_CR0 TIMER_CR0(TIMER2) |
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#define TIMER3_CR0 TIMER_CR0(TIMER3) |
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/* Capture Register 1 */ |
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#define TIMER_CR1(timer) MMIO32(timer + 0x030) |
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#define TIMER0_CR1 TIMER_CR1(TIMER0) |
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#define TIMER1_CR1 TIMER_CR1(TIMER1) |
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#define TIMER2_CR1 TIMER_CR1(TIMER2) |
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#define TIMER3_CR1 TIMER_CR1(TIMER3) |
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/* Capture Register 2 */ |
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#define TIMER_CR2(timer) MMIO32(timer + 0x034) |
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#define TIMER0_CR2 TIMER_CR2(TIMER0) |
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#define TIMER1_CR2 TIMER_CR2(TIMER1) |
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#define TIMER2_CR2 TIMER_CR2(TIMER2) |
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#define TIMER3_CR2 TIMER_CR2(TIMER3) |
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/* Capture Register 3 */ |
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#define TIMER_CR3(timer) MMIO32(timer + 0x038) |
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#define TIMER0_CR3 TIMER_CR3(TIMER0) |
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#define TIMER1_CR3 TIMER_CR3(TIMER1) |
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#define TIMER2_CR3 TIMER_CR3(TIMER2) |
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#define TIMER3_CR3 TIMER_CR3(TIMER3) |
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/* External Match Register */ |
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#define TIMER_EMR(timer) MMIO32(timer + 0x03C) |
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#define TIMER0_EMR TIMER_EMR(TIMER0) |
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#define TIMER1_EMR TIMER_EMR(TIMER1) |
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#define TIMER2_EMR TIMER_EMR(TIMER2) |
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#define TIMER3_EMR TIMER_EMR(TIMER3) |
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/* Count Control Register */ |
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#define TIMER_CTCR(timer) MMIO32(timer + 0x070) |
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#define TIMER0_CTCR TIMER_CTCR(TIMER0) |
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#define TIMER1_CTCR TIMER_CTCR(TIMER1) |
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#define TIMER2_CTCR TIMER_CTCR(TIMER2) |
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#define TIMER3_CTCR TIMER_CTCR(TIMER3) |
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#endif |
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