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stm32f4: Add QUADSPI Includes 

Adds an include file (and required RCC and memorymap changes)
to address registers in the QUADSPI peripheral on the F4 line
of processors.
pull/683/merge
Chuck McManis 8 years ago
committed by Karl Palsson
parent
32f2b5042f
commit
32a91e52ff
4 changed files with 205 additions and 1 deletions
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  1. 17
      include/libopencm3/stm32/f4/memorymap.h
  2. 159
      include/libopencm3/stm32/f4/quadspi.h
  3. 2
      include/libopencm3/stm32/f4/rcc.h
  4. 28
      include/libopencm3/stm32/quadspi.h

17
include/libopencm3/stm32/f4/memorymap.h
View File

@ -96,7 +96,8 @@
#define SPI6_BASE (PERIPH_BASE_APB2 + 0x5400) #define SPI6_BASE (PERIPH_BASE_APB2 + 0x5400)
#define SAI1_BASE (PERIPH_BASE_APB2 + 0x5800) #define SAI1_BASE (PERIPH_BASE_APB2 + 0x5800)
#define LTDC_BASE (PERIPH_BASE_APB2 + 0x6800) #define LTDC_BASE (PERIPH_BASE_APB2 + 0x6800)
/* PERIPH_BASE_APB2 + 0x6C00 (0x4001 6C00 - 0x4001 FFFF): Reserved */ #define DSI_BASE (PERIPH_BASE_APB2 + 0x6C00)
/* PERIPH_BASE_APB2 + 0x7400 (0x4001 7400 - 0x4001 FFFF): Reserved */
/* AHB1 */ /* AHB1 */
#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB1 + 0x0000) #define GPIO_PORT_A_BASE (PERIPH_BASE_AHB1 + 0x0000)
@ -137,7 +138,21 @@
/* PERIPH_BASE_AHB2 + 0x61000 (0x5006 1000 - 0x5FFF FFFF): Reserved */ /* PERIPH_BASE_AHB2 + 0x61000 (0x5006 1000 - 0x5FFF FFFF): Reserved */
/* AHB3 */ /* AHB3 */
/* Address: 0x60000000 */
#define FMC_BANK1 (PERIPH_BASE_AHB3)
/* Address: 0x70000000 */
#define FMC_BANK2 (PERIPH_BASE_AHB3 + 0x10000000U)
/* Address: 0x80000000 */
#define FMC_BANK3 (PERIPH_BASE_AHB3 + 0x20000000U)
/* Address: 0x90000000 */
#define QUADSPI_BANK (PERIPH_BASE_AHB3 + 0x30000000U)
#define FSMC_BASE (PERIPH_BASE_AHB3 + 0x40000000U) #define FSMC_BASE (PERIPH_BASE_AHB3 + 0x40000000U)
#define FMC_BASE (PERIPH_BASE_AHB3 + 0x40000000U)
#define QUADSPI_BASE (PERIPH_BASE_AHB3 + 0x40001000U)
/* Address: 0xC0000000 */
#define FMC_BANK5 (PERIPH_BASE_AHB3 + 0x60000000U)
/* Address: 0xD0000000 */
#define FMC_BANK6 (PERIPH_BASE_AHB3 + 0x70000000U)
/* PPIB */ /* PPIB */
#define DBGMCU_BASE (PPBI_BASE + 0x00042000) #define DBGMCU_BASE (PPBI_BASE + 0x00042000)

159
include/libopencm3/stm32/f4/quadspi.h
View File

@ -0,0 +1,159 @@
/*
* STM32F4 Quad SPI defines
*
* Copyright (C) 2016, Chuck McManis <cmcmanis@mcmanis.com>
*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*
*/
#include <libopencm3/stm32/memorymap.h>
/* QUADSPI Control register */
#define QUADSPI_CR MMIO32(QUADSPI_BASE + 0x0U)
#define QUADSPI_CR_PRESCALE_MASK 0xff
#define QUADSPI_CR_PRESCALE_SHIFT 24
#define QUADSPI_CR_PMM (1 << 23)
#define QUADSPI_CR_APMS (1 << 22)
/* bit 21 is reserved */
#define QUADSPI_CR_TOIE (1 << 20)
#define QUADSPI_CR_SMIE (1 << 19)
#define QUADSPI_CR_FTIE (1 << 18)
#define QUADSPI_CR_TCIE (1 << 17)
#define QUADSPI_CR_TEIE (1 << 16)
/* bits 15:13 reserved */
#define QUADSPI_CR_FTHRES_MASK 0x1f
#define QUADSPI_CR_FTHRES_SHIFT 8
#define QUADSPI_CR_FSEL (1 << 7)
#define QUADSPI_CR_DFM (1 << 6)
/* bit 5 reserved */
#define QUADSPI_CR_SSHIFT (1 << 4)
#define QUADSPI_CR_TCEN (1 << 3)
#define QUADSPI_CR_DMAEN (1 << 2)
#define QUADSPI_CR_ABORT (1 << 1)
#define QUADSPI_CR_EN (1 << 0)
/* QUADSPI Device Configuration */
#define QUADSPI_DCR MMIO32(QUADSPI_BASE + 0x4U)
/* bits 31:21 reserved */
#define QUADSPI_DCR_FSIZE_MASK 0x1f
#define QUADSPI_DCR_FSIZE_SHIFT 16
/* bits 15:11 reserved */
#define QUADSPI_DCR_CSHT_MASK 0x7
#define QUADSPI_DCR_CSHT_SHIFT 8
/* bits 7:1 reserved */
#define QUADSPI_DCR_CKMODE (1 << 0)
/* QUADSPI Status Register */
#define QUADSPI_SR MMIO32(QUADSPI_BASE + 0x8U)
/* bits 31:14 reserved */
#define QUADSPI_SR_FLEVEL_MASK 0x3f
#define QUADSPI_SR_FLEVEL_SHIFT 8
/* bits 7:6 reserved */
#define QUADSPI_SR_BUSY (1 << 5)
#define QUADSPI_SR_TOF (1 << 4)
#define QUADSPI_SR_SMF (1 << 3)
#define QUADSPI_SR_FTF (1 << 2)
#define QUADSPI_SR_TCF (1 << 1)
#define QUADSPI_SR_TEF (1 << 0)
/* QUADSPI Flag Clear Register */
#define QUADSPI_FCR MMIO32(QUADSPI_BASE + 0xCU)
/* bits 31:5 reserved */
#define QUADSPI_FCR_CTOF (1 << 4)
#define QUADSPI_FCR_CSMF (1 << 3)
/* bit 2 reserved */
#define QUADSPI_FCR_CTCF (1 << 1)
#define QUADSPI_FCR_CTEF (1 << 0)
/* QUADSPI Data Length Register */
#define QUADSPI_DLR MMIO32(QUADSPI_BASE + 0x10U)
/* QUADSPI Communication Configuration Register */
#define QUADSPI_CCR MMIO32(QUADSPI_BASE + 0x14U)
#define QUADSPI_CCR_DDRM (1 << 31)
#define QUADSPI_CCR_DHHC (1 << 30)
/* bit 29 reserved */
#define QUADSPI_CCR_SIOO (1 << 28)
#define QUADSPI_CCR_FMODE_MASK 0x3
#define QUADSPI_CCR_FMODE_SHIFT 26
#define QUADSPI_CCR_DMODE_MASK 0x3
#define QUADSPI_CCR_DMODE_SHIFT 24
/* bit 23 reserved */
#define QUADSPI_CCR_DCYC_MASK 0x1f
#define QUADSPI_CCR_DCYC_SHIFT 18
#define QUADSPI_CCR_ABSIZE_MASK 0x3
#define QUADSPI_CCR_ABSIZE_SHIFT 16
#define QUADSPI_CCR_ABMODE_MASK 0x3
#define QUADSPI_CCR_ABMODE_SHIFT 14
#define QUADSPI_CCR_ADSIZE_MASK 0x3
#define QUADSPI_CCR_ADSIZE_SHIFT 12
#define QUADSPI_CCR_ADMODE_MASK 0x3
#define QUADSPI_CCR_ADMODE_SHIFT 10
#define QUADSPI_CCR_IMODE_MASK 0x3
#define QUADSPI_CCR_IMODE_SHIFT 8
#define QUADSPI_CCR_INST_MASK 0xff
#define QUADSPI_CCR_INST_SHIFT 0
/* MODE values */
#define QUADSPI_CCR_MODE_NONE 0
#define QUADSPI_CCR_MODE_1LINE 1
#define QUADSPI_CCR_MODE_2LINE 2
#define QUADSPI_CCR_MODE_4LINE 3
/* FMODE values */
#define QUADSPI_CCR_FMODE_IWRITE 0
#define QUADSPI_CCR_FMODE_IREAD 1
#define QUADSPI_CCR_FMODE_APOLL 2
#define QUADSPI_CCR_FMODE_MEMMAP 3
/* QUADSPI address register */
#define QUADSPI_AR MMIO32(QUADSPI_BASE + 0x18U)
/* QUADSPI alternate bytes register */
#define QUADSPI_ABR MMI032(QUADSPI_BASE + 0x1CU)
/* QUADSPI data register */
#define QUADSPI_DR MMIO32(QUADSPI_BASE + 0x20U)
/* BYTE addressable version for fetching bytes from the interface */
#define QUADSPI_BYTE_DR MMIO8(QUADSPI_BASE + 0x20U)
/* QUADSPI polling status */
#define QUADSPI_PSMKR MMIO32(QUADSPI_BASE + 0x24U)
/* QUADSPI polling status match */
#define QUADSPI_PSMAR MMIO32(QUADSPI_BASE + 0x28U)
/* QUADSPI polling interval register */
#define QUADSPI_PIR MMIO32(QUADSPI_BASE + 0x2CU)
/* QUADSPI low power timeout */
#define QUADSPI_LPTR MMIO32(QUADSPI_BASE + 0x30U)

2
include/libopencm3/stm32/f4/rcc.h
View File

@ -710,6 +710,8 @@ enum rcc_periph_clken {
/* AHB3 peripherals */ /* AHB3 peripherals */
RCC_FSMC = _REG_BIT(0x38, 0), RCC_FSMC = _REG_BIT(0x38, 0),
RCC_FMC = _REG_BIT(0x38, 0),
RCC_QUADSPI = _REG_BIT(0x38, 1),
/* APB1 peripherals*/ /* APB1 peripherals*/
RCC_TIM2 = _REG_BIT(0x40, 0), RCC_TIM2 = _REG_BIT(0x40, 0),

28
include/libopencm3/stm32/quadspi.h
View File

@ -0,0 +1,28 @@
/* This provides unification of code over STM32 subfamilies */
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#include <libopencm3/cm3/common.h>
#include <libopencm3/stm32/memorymap.h>
#if defined(STM32F4)
# include <libopencm3/stm32/f4/quadspi.h>
#else
# error "quadspi.h not available for this family."
#endif
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