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@ -533,8 +533,8 @@ |
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/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in
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* TIMx_CCER). */ |
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#define TIM_CCMR1_CC1S_OUT (0x0 << 0) |
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#define TIM_CCMR1_CC1S_IN_TI2 (0x1 << 0) |
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#define TIM_CCMR1_CC1S_IN_TI1 (0x2 << 0) |
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#define TIM_CCMR1_CC1S_IN_TI2 (0x2 << 0) |
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#define TIM_CCMR1_CC1S_IN_TI1 (0x1 << 0) |
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#define TIM_CCMR1_CC1S_IN_TRC (0x3 << 0) |
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#define TIM_CCMR1_CC1S_MASK (0x3 << 0) |
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