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usb: Coding-style fixes.

pull/2/head
Uwe Hermann 13 years ago
parent
d97c937b8e
commit
3e9b9cb345
5 changed files with 129 additions and 120 deletions
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  1. 4
      lib/usb/usb.c
  2. 3
      lib/usb/usb_control.c
  3. 9
      lib/usb/usb_f103.c
  4. 151
      lib/usb/usb_f107.c
  5. 24
      lib/usb/usb_standard.c

4
lib/usb/usb.c
View File

@ -107,8 +107,7 @@ void usbd_poll(void)
_usbd_device.driver->poll();
}
void usbd_ep_setup(u8 addr, u8 type, u16 max_size,
void (*callback)(u8 ep))
void usbd_ep_setup(u8 addr, u8 type, u16 max_size, void (*callback)(u8 ep))
{
_usbd_device.driver->ep_setup(addr, type, max_size, callback);
}
@ -137,4 +136,3 @@ void usbd_ep_nak_set(u8 addr, u8 nak)
{
_usbd_device.driver->ep_nak_set(addr, nak);
}

3
lib/usb/usb_control.c
View File

@ -186,7 +186,8 @@ void _usbd_control_out(u8 ea)
case LAST_DATA_OUT:
if (usb_control_recv_chunk() < 0)
break;
/* We have now received the full data payload.
/*
* We have now received the full data payload.
* Invoke callback to process.
*/
if (usb_control_request_dispatch(&control_state.req)) {

9
lib/usb/usb_f103.c
View File

@ -185,13 +185,13 @@ static u8 stm32f103_ep_stall_get(u8 addr)
static void stm32f103_ep_nak_set(u8 addr, u8 nak)
{
/* It does not make sence to force NAK on IN endpoints */
if(addr & 0x80)
/* It does not make sence to force NAK on IN endpoints. */
if (addr & 0x80)
return;
force_nak[addr] = nak;
if(nak)
if (nak)
USB_SET_EP_RX_STAT(addr, USB_EP_RX_STAT_NAK);
else
USB_SET_EP_RX_STAT(addr, USB_EP_RX_STAT_VALID);
@ -256,7 +256,7 @@ static u16 stm32f103_ep_read_packet(u8 addr, void *buf, u16 len)
usb_copy_from_pm(buf, USB_GET_EP_RX_BUFF(addr), len);
USB_CLR_EP_RX_CTR(addr);
if(!force_nak[addr])
if (!force_nak[addr])
USB_SET_EP_RX_STAT(addr, USB_EP_RX_STAT_VALID);
return len;
@ -306,4 +306,3 @@ static void stm32f103_poll(void)
USB_CLR_ISTR_SOF();
}
}

151
lib/usb/usb_f107.c
View File

@ -17,6 +17,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <string.h>
#include <libopencm3/stm32/f1/rcc.h>
#include <libopencm3/cm3/common.h>
#include <libopencm3/stm32/tools.h>
@ -24,9 +25,7 @@
#include <libopencm3/usb/usbd.h>
#include "usb_private.h"
#include <string.h>
/* Receive FIFO size in 32-bit words */
/* Receive FIFO size in 32-bit words. */
#define RX_FIFO_SIZE 128
static uint16_t fifo_mem_top;
static uint16_t fifo_mem_top_ep0;
@ -36,7 +35,7 @@ static u8 force_nak[4];
static void stm32f107_usbd_init(void);
static void stm32f107_set_address(u8 addr);
static void stm32f107_ep_setup(u8 addr, u8 type, u16 max_size,
void (*callback) (u8 ep));
void (*callback)(u8 ep));
static void stm32f107_endpoints_reset(void);
static void stm32f107_ep_stall_set(u8 addr, u8 stall);
static u8 stm32f107_ep_stall_get(u8 addr);
@ -45,8 +44,10 @@ static u16 stm32f107_ep_write_packet(u8 addr, const void *buf, u16 len);
static u16 stm32f107_ep_read_packet(u8 addr, void *buf, u16 len);
static void stm32f107_poll(void);
/* We keep a backup copy of the out endpoint size registers to restore them
* after a transaction */
/*
* We keep a backup copy of the out endpoint size registers to restore them
* after a transaction.
*/
static u32 doeptsiz[4];
const struct _usbd_driver stm32f107_usb_driver = {
@ -69,30 +70,28 @@ static void stm32f107_usbd_init(void)
OTG_FS_GINTSTS = OTG_FS_GINTSTS_MMIS;
OTG_FS_GUSBCFG |= OTG_FS_GUSBCFG_PHYSEL;
/* Enable VBUS sensing in device mode and power down the phy */
/* Enable VBUS sensing in device mode and power down the PHY. */
OTG_FS_GCCFG |= OTG_FS_GCCFG_VBUSBSEN | OTG_FS_GCCFG_PWRDWN;
/* Wait for AHB idle */
while(!(OTG_FS_GRSTCTL & OTG_FS_GRSTCTL_AHBIDL));
/* Do core soft reset */
/* Wait for AHB idle. */
while (!(OTG_FS_GRSTCTL & OTG_FS_GRSTCTL_AHBIDL)) ;
/* Do core soft reset. */
OTG_FS_GRSTCTL |= OTG_FS_GRSTCTL_CSRST;
while(OTG_FS_GRSTCTL & OTG_FS_GRSTCTL_CSRST);
while (OTG_FS_GRSTCTL & OTG_FS_GRSTCTL_CSRST) ;
/* Force peripheral only mode. */
OTG_FS_GUSBCFG |= OTG_FS_GUSBCFG_FDMOD | OTG_FS_GUSBCFG_TRDT_MASK;
/* Full speed device */
/* Full speed device. */
OTG_FS_DCFG |= OTG_FS_DCFG_DSPD;
/* Restart the phy clock */
/* Restart the PHY clock. */
OTG_FS_PCGCCTL = 0;
OTG_FS_GRXFSIZ = RX_FIFO_SIZE;
fifo_mem_top = RX_FIFO_SIZE;
/* Unmask interrupts for TX and RX */
/* Unmask interrupts for TX and RX. */
OTG_FS_GAHBCFG |= OTG_FS_GAHBCFG_GINT;
OTG_FS_GINTMSK = OTG_FS_GINTMSK_ENUMDNEM |
OTG_FS_GINTMSK_RXFLVLM |
@ -112,20 +111,20 @@ static void stm32f107_set_address(u8 addr)
static void stm32f107_ep_setup(u8 addr, u8 type, u16 max_size,
void (*callback) (u8 ep))
{
/* Configure endpoint address and type.
* Allocate FIFO memory for endpoint.
* Install callback funciton.
/*
* Configure endpoint address and type. Allocate FIFO memory for
* endpoint. Install callback funciton.
*/
u8 dir = addr & 0x80;
addr &= 0x7f;
if(addr == 0) { /* For the default control endpoint */
/* Configure IN part */
if(max_size >= 64) {
if (addr == 0) { /* For the default control endpoint */
/* Configure IN part. */
if (max_size >= 64) {
OTG_FS_DIEPCTL0 = OTG_FS_DIEPCTL0_MPSIZ_64;
} else if(max_size >= 32) {
} else if (max_size >= 32) {
OTG_FS_DIEPCTL0 = OTG_FS_DIEPCTL0_MPSIZ_32;
} else if(max_size >= 16) {
} else if (max_size >= 16) {
OTG_FS_DIEPCTL0 = OTG_FS_DIEPCTL0_MPSIZ_16;
} else {
OTG_FS_DIEPCTL0 = OTG_FS_DIEPCTL0_MPSIZ_8;
@ -133,11 +132,12 @@ static void stm32f107_ep_setup(u8 addr, u8 type, u16 max_size,
OTG_FS_DIEPTSIZ0 = (max_size & OTG_FS_DIEPSIZ0_XFRSIZ_MASK);
OTG_FS_DIEPCTL0 |= OTG_FS_DIEPCTL0_EPENA | OTG_FS_DIEPCTL0_SNAK;
/* Configure OUT part */
/* Configure OUT part. */
doeptsiz[0] = OTG_FS_DIEPSIZ0_STUPCNT_1 | (1 << 19) |
(max_size & OTG_FS_DIEPSIZ0_XFRSIZ_MASK);
OTG_FS_DOEPTSIZ(0) = doeptsiz[0];
OTG_FS_DOEPCTL(0) |= OTG_FS_DOEPCTL0_EPENA | OTG_FS_DIEPCTL0_SNAK;
OTG_FS_DOEPCTL(0) |=
OTG_FS_DOEPCTL0_EPENA | OTG_FS_DIEPCTL0_SNAK;
OTG_FS_GNPTXFSIZ = ((max_size / 4) << 16) | RX_FIFO_SIZE;
fifo_mem_top += max_size / 4;
@ -150,11 +150,12 @@ static void stm32f107_ep_setup(u8 addr, u8 type, u16 max_size,
OTG_FS_DIEPTXF(addr) = ((max_size / 4) << 16) | fifo_mem_top;
fifo_mem_top += max_size / 4;
OTG_FS_DIEPTSIZ(addr) = (max_size & OTG_FS_DIEPSIZ0_XFRSIZ_MASK);
OTG_FS_DIEPCTL(addr) |= OTG_FS_DIEPCTL0_EPENA |
OTG_FS_DIEPCTL0_SNAK | (type << 18) |
OTG_FS_DIEPCTL0_USBAEP | OTG_FS_DIEPCTLX_SD0PID |
(addr << 22) | max_size;
OTG_FS_DIEPTSIZ(addr) =
(max_size & OTG_FS_DIEPSIZ0_XFRSIZ_MASK);
OTG_FS_DIEPCTL(addr) |=
OTG_FS_DIEPCTL0_EPENA | OTG_FS_DIEPCTL0_SNAK | (type << 18)
| OTG_FS_DIEPCTL0_USBAEP | OTG_FS_DIEPCTLX_SD0PID
| (addr << 22) | max_size;
if (callback) {
_usbd_device.
@ -169,8 +170,7 @@ static void stm32f107_ep_setup(u8 addr, u8 type, u16 max_size,
OTG_FS_DOEPTSIZ(addr) = doeptsiz[addr];
OTG_FS_DOEPCTL(addr) |= OTG_FS_DOEPCTL0_EPENA |
OTG_FS_DOEPCTL0_USBAEP | OTG_FS_DIEPCTL0_CNAK |
OTG_FS_DOEPCTLX_SD0PID |
(type << 18) | max_size;
OTG_FS_DOEPCTLX_SD0PID | (type << 18) | max_size;
if (callback) {
_usbd_device.
@ -182,30 +182,30 @@ static void stm32f107_ep_setup(u8 addr, u8 type, u16 max_size,
static void stm32f107_endpoints_reset(void)
{
/* The core resets the endpoints automatically on reset */
/* The core resets the endpoints automatically on reset. */
fifo_mem_top = fifo_mem_top_ep0;
}
static void stm32f107_ep_stall_set(u8 addr, u8 stall)
{
if(addr == 0) {
if(stall)
if (addr == 0) {
if (stall)
OTG_FS_DIEPCTL(addr) |= OTG_FS_DIEPCTL0_STALL;
else
OTG_FS_DIEPCTL(addr) &= ~OTG_FS_DIEPCTL0_STALL;
}
if(addr & 0x80) {
if (addr & 0x80) {
addr &= 0x7F;
if(stall) {
if (stall) {
OTG_FS_DIEPCTL(addr) |= OTG_FS_DIEPCTL0_STALL;
} else {
OTG_FS_DIEPCTL(addr) &= ~OTG_FS_DIEPCTL0_STALL;
OTG_FS_DIEPCTL(addr) |= OTG_FS_DIEPCTLX_SD0PID;
}
} else {
if(stall) {
if (stall) {
OTG_FS_DOEPCTL(addr) |= OTG_FS_DOEPCTL0_STALL;
} else {
OTG_FS_DOEPCTL(addr) &= ~OTG_FS_DOEPCTL0_STALL;
@ -216,22 +216,23 @@ static void stm32f107_ep_stall_set(u8 addr, u8 stall)
static u8 stm32f107_ep_stall_get(u8 addr)
{
/* return non-zero if STALL set. */
if(addr & 0x80)
return (OTG_FS_DIEPCTL(addr&0x7f) & OTG_FS_DIEPCTL0_STALL)?1:0;
/* Return non-zero if STALL set. */
if (addr & 0x80)
return
(OTG_FS_DIEPCTL(addr & 0x7f) & OTG_FS_DIEPCTL0_STALL) ? 1 : 0;
else
return (OTG_FS_DOEPCTL(addr) & OTG_FS_DOEPCTL0_STALL)?1:0;
return (OTG_FS_DOEPCTL(addr) & OTG_FS_DOEPCTL0_STALL) ? 1 : 0;
}
static void stm32f107_ep_nak_set(u8 addr, u8 nak)
{
/* It does not make sence to force NAK on IN endpoints */
if(addr & 0x80)
/* It does not make sence to force NAK on IN endpoints. */
if (addr & 0x80)
return;
force_nak[addr] = nak;
if(nak)
if (nak)
OTG_FS_DOEPCTL(addr) |= OTG_FS_DOEPCTL0_SNAK;
else
OTG_FS_DOEPCTL(addr) |= OTG_FS_DOEPCTL0_CNAK;
@ -245,23 +246,23 @@ static u16 stm32f107_ep_write_packet(u8 addr, const void *buf, u16 len)
addr &= 0x7F;
/* Return if endpoint is already enabled. */
if(OTG_FS_DIEPTSIZ(addr) & OTG_FS_DIEPSIZ0_PKTCNT)
if (OTG_FS_DIEPTSIZ(addr) & OTG_FS_DIEPSIZ0_PKTCNT)
return 0;
/* Enable endpoint for transmission */
/* Enable endpoint for transmission. */
OTG_FS_DIEPTSIZ(addr) = (1 << 19) | len;
OTG_FS_DIEPCTL(addr) |= OTG_FS_DIEPCTL0_EPENA | OTG_FS_DIEPCTL0_CNAK;
/* Copy buffer to endpoint FIFO */
/* Copy buffer to endpoint FIFO. */
volatile u32 *fifo = OTG_FS_FIFO(addr);
for(i = len; i > 0; i -= 4) {
for (i = len; i > 0; i -= 4)
*fifo++ = *buf32++;
}
return len;
}
/* Received packet size for each endpoint. This is assigned in
/*
* Received packet size for each endpoint. This is assigned in
* stm32f107_poll() which reads the packet status push register GRXSTSP
* for use in stm32f107_ep_read_packet().
*/
@ -277,11 +278,10 @@ static u16 stm32f107_ep_read_packet(u8 addr, void *buf, u16 len)
rxbcnt -= len;
volatile u32 *fifo = OTG_FS_FIFO(addr);
for(i = len; i >= 4; i -= 4) {
for (i = len; i >= 4; i -= 4)
*buf32++ = *fifo++;
}
if(i) {
if (i) {
extra = *fifo++;
memcpy(buf32, &extra, i);
}
@ -295,12 +295,12 @@ static u16 stm32f107_ep_read_packet(u8 addr, void *buf, u16 len)
static void stm32f107_poll(void)
{
/* Read interrupt status register */
/* Read interrupt status register. */
u32 intsts = OTG_FS_GINTSTS;
int i;
if (intsts & OTG_FS_GINTSTS_ENUMDNE) {
/* Handle USB RESET condition */
/* Handle USB RESET condition. */
OTG_FS_GINTSTS = OTG_FS_GINTSTS_ENUMDNE;
fifo_mem_top = RX_FIFO_SIZE;
_usbd_reset();
@ -309,47 +309,53 @@ static void stm32f107_poll(void)
/* Note: RX and TX handled differently in this device. */
if (intsts & OTG_FS_GINTSTS_RXFLVL) {
/* Receive FIFO non-empty */
/* Receive FIFO non-empty. */
u32 rxstsp = OTG_FS_GRXSTSP;
u32 pktsts = rxstsp & OTG_FS_GRXSTSP_PKTSTS_MASK;
if((pktsts != OTG_FS_GRXSTSP_PKTSTS_OUT) &&
if ((pktsts != OTG_FS_GRXSTSP_PKTSTS_OUT) &&
(pktsts != OTG_FS_GRXSTSP_PKTSTS_SETUP))
return;
u8 ep = rxstsp & OTG_FS_GRXSTSP_EPNUM_MASK;
u8 type;
if(pktsts == OTG_FS_GRXSTSP_PKTSTS_SETUP)
if (pktsts == OTG_FS_GRXSTSP_PKTSTS_SETUP)
type = USB_TRANSACTION_SETUP;
else
type = USB_TRANSACTION_OUT;
/* Save packet size for stm32f107_ep_read_packet() */
/* Save packet size for stm32f107_ep_read_packet(). */
rxbcnt = (rxstsp & OTG_FS_GRXSTSP_BCNT_MASK) >> 4;
/* FIXME: Why is a delay needed here?
/*
* FIXME: Why is a delay needed here?
* This appears to fix a problem where the first 4 bytes
* of the DATA OUT stage of a control transaction are lost.
*/
for(i = 0; i < 1000; i++) asm("nop");
for (i = 0; i < 1000; i++)
__asm__("nop");
if (_usbd_device.user_callback_ctr[ep][type])
_usbd_device.user_callback_ctr[ep][type] (ep);
/* Discard unread packet data */
for(i = 0; i < rxbcnt; i += 4)
/* Discard unread packet data. */
for (i = 0; i < rxbcnt; i += 4)
(void)*OTG_FS_FIFO(ep);
rxbcnt = 0;
}
/* There is no global interrupt flag for transmit complete.
* the XFRC bit must be checked in each OTG_FS_DIEPINT(x)
/*
* There is no global interrupt flag for transmit complete.
* The XFRC bit must be checked in each OTG_FS_DIEPINT(x).
*/
for (i = 0; i < 4; i++) { /* Iterate over endpoints */
if(OTG_FS_DIEPINT(i) & OTG_FS_DIEPINTX_XFRC) {
/* Transfer complete */
if (_usbd_device.user_callback_ctr[i][USB_TRANSACTION_IN])
_usbd_device.user_callback_ctr[i][USB_TRANSACTION_IN] (i);
for (i = 0; i < 4; i++) { /* Iterate over endpoints. */
if (OTG_FS_DIEPINT(i) & OTG_FS_DIEPINTX_XFRC) {
/* Transfer complete. */
if (_usbd_device.
user_callback_ctr[i][USB_TRANSACTION_IN]) {
_usbd_device.
user_callback_ctr[i][USB_TRANSACTION_IN](i);
}
OTG_FS_DIEPINT(i) = OTG_FS_DIEPINTX_XFRC;
}
}
@ -372,4 +378,3 @@ static void stm32f107_poll(void)
OTG_FS_GINTSTS = OTG_FS_GINTSTS_SOF;
}
}

24
lib/usb/usb_standard.c
View File

@ -98,9 +98,9 @@ static int usb_standard_get_descriptor(struct usb_setup_data *req,
if (!_usbd_device.strings)
return 0; /* Device doesn't support strings. */
/* Check that string index is in range */
for(i = 0; i <= (req->wValue & 0xff); i++)
if(_usbd_device.strings[i] == NULL)
/* Check that string index is in range. */
for (i = 0; i <= (req->wValue & 0xff); i++)
if (_usbd_device.strings[i] == NULL)
return 0;
sd->bLength = strlen(_usbd_device.strings[req->wValue & 0xff])
@ -136,10 +136,11 @@ static int usb_standard_set_address(struct usb_setup_data *req, u8 **buf,
_usbd_device.current_address = req->wValue;
/* Special workaround for STM32F10[57] that require the address
/*
* Special workaround for STM32F10[57] that require the address
* to be set here. This is undocumented!
*/
if(_usbd_device.driver == &stm32f107_usb_driver)
if (_usbd_device.driver == &stm32f107_usb_driver)
_usbd_device.driver->set_address(req->wValue);
return 1;
@ -220,6 +221,7 @@ static int usb_standard_device_get_status(struct usb_setup_data *req,
u8 **buf, u16 *len)
{
(void)req;
/* bit 0: self powered */
/* bit 1: remote wakeup */
if (*len > 2)
@ -311,8 +313,10 @@ int _usbd_standard_request_device(struct usb_setup_data *req, u8 **buf,
command = usb_standard_get_descriptor;
break;
case USB_REQ_GET_STATUS:
/* GET_STATUS always responds with zero reply.
* The application may override this behaviour. */
/*
* GET_STATUS always responds with zero reply.
* The application may override this behaviour.
*/
command = usb_standard_device_get_status;
break;
case USB_REQ_SET_DESCRIPTOR:
@ -372,8 +376,10 @@ int _usbd_standard_request_endpoint(struct usb_setup_data *req, u8 **buf,
break;
case USB_REQ_SET_SYNCH_FRAME:
/* FIXME: SYNCH_FRAME is not implemented. */
/* SYNCH_FRAME is used for synchronization of isochronous
* endpoints which are not yet implemented. */
/*
* SYNCH_FRAME is used for synchronization of isochronous
* endpoints which are not yet implemented.
*/
break;
}

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