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@ -30,15 +30,10 @@ void ipc_halt_m0(void) |
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rst_active_status1 = RESET_ACTIVE_STATUS1; |
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/* If the M0 has reset not asserted, halt it... */ |
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if( (rst_active_status1 & RESET_CTRL1_M0APP_RST) ) |
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while( (rst_active_status1 & RESET_CTRL1_M0APP_RST) ) |
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{ |
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RESET_CTRL1 = ((~rst_active_status1) | RESET_CTRL1_M0APP_RST); |
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rst_active_status1 = RESET_ACTIVE_STATUS1; |
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/* Check again */ |
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if( (rst_active_status1 & RESET_CTRL1_M0APP_RST) ) |
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{ |
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RESET_CTRL1 = ((~rst_active_status1) | RESET_CTRL1_M0APP_RST); |
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} |
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} |
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} |
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@ -56,15 +51,10 @@ void ipc_start_m0(u32 cm0_baseaddr) |
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/* If the M0 is being held in reset, release it */ |
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/* 1 = no reset, 0 = reset */ |
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if( !(rst_active_status1 & RESET_CTRL1_M0APP_RST) ) |
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while( !(rst_active_status1 & RESET_CTRL1_M0APP_RST) ) |
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{ |
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RESET_CTRL1 = ((~rst_active_status1) & (~RESET_CTRL1_M0APP_RST)); |
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rst_active_status1 = RESET_ACTIVE_STATUS1; |
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/* Check again */ |
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if( !(rst_active_status1 & RESET_CTRL1_M0APP_RST) ) |
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{ |
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RESET_CTRL1 = ((~rst_active_status1) & (~RESET_CTRL1_M0APP_RST)); |
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} |
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} |
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} |
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