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@ -0,0 +1,935 @@ |
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/** @defgroup rcc_defines RCC Defines
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* |
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* @ingroup STM32G4xx_defines |
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* |
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* @brief <b>Defined Constants and Types for the STM32G4xx Reset and Clock |
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* Control</b> |
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* |
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* @version 1.0.0 |
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* |
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* @author @htmlonly © @endhtmlonly 2020 Karl Palsson <karlp@tweak.net.au> |
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* |
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* LGPL License Terms @ref lgpl_license |
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*/ |
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/*
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* This file is part of the libopencm3 project. |
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* |
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* Copyright (C) 2020 Karl Palsson <karlp@tweak.net.au> |
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* |
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* This library is free software: you can redistribute it and/or modify |
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* it under the terms of the GNU Lesser General Public License as published by |
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* the Free Software Foundation, either version 3 of the License, or |
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* (at your option) any later version. |
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* |
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* This library is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU Lesser General Public License for more details. |
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* |
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* You should have received a copy of the GNU Lesser General Public License |
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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* |
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*/ |
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/**@{*/ |
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#ifndef LIBOPENCM3_RCC_H |
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#define LIBOPENCM3_RCC_H |
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/** @defgroup rcc_registers RCC Registers
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* @{ |
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*/ |
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#define RCC_CR MMIO32(RCC_BASE + 0x00) |
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#define RCC_ICSCR MMIO32(RCC_BASE + 0x04) |
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#define RCC_CFGR MMIO32(RCC_BASE + 0x08) |
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#define RCC_PLLCFGR MMIO32(RCC_BASE + 0x0c) |
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#define RCC_CIER MMIO32(RCC_BASE + 0x18) |
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#define RCC_CIFR MMIO32(RCC_BASE + 0x1c) |
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#define RCC_CICR MMIO32(RCC_BASE + 0x20) |
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#define RCC_AHB1RSTR MMIO32(RCC_BASE + 0x28) |
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#define RCC_AHB2RSTR MMIO32(RCC_BASE + 0x2c) |
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#define RCC_AHB3RSTR MMIO32(RCC_BASE + 0x30) |
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#define RCC_APB1RSTR1 MMIO32(RCC_BASE + 0x38) |
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#define RCC_APB1RSTR2 MMIO32(RCC_BASE + 0x3c) |
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#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x40) |
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#define RCC_AHB1ENR MMIO32(RCC_BASE + 0x48) |
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#define RCC_AHB2ENR MMIO32(RCC_BASE + 0x4c) |
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#define RCC_AHB3ENR MMIO32(RCC_BASE + 0x50) |
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#define RCC_APB1ENR1 MMIO32(RCC_BASE + 0x58) |
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#define RCC_APB1ENR2 MMIO32(RCC_BASE + 0x5c) |
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#define RCC_APB2ENR MMIO32(RCC_BASE + 0x60) |
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#define RCC_AHB1SMENR MMIO32(RCC_BASE + 0x68) |
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#define RCC_AHB2SMENR MMIO32(RCC_BASE + 0x6c) |
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#define RCC_AHB3SMENR MMIO32(RCC_BASE + 0x70) |
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#define RCC_APB1SMENR1 MMIO32(RCC_BASE + 0x78) |
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#define RCC_APB1SMENR2 MMIO32(RCC_BASE + 0x7c) |
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#define RCC_APB2SMENR MMIO32(RCC_BASE + 0x80) |
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#define RCC_CCIPR MMIO32(RCC_BASE + 0x88) |
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#define RCC_BDCR MMIO32(RCC_BASE + 0x90) |
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#define RCC_CSR MMIO32(RCC_BASE + 0x94) |
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#define RCC_CRRCR MMIO32(RCC_BASE + 0x98) |
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#define RCC_CCIPR2 MMIO32(RCC_BASE + 0x9c) |
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/**@}*/ |
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/** @defgroup rcc_cr_values RCC_CR values
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* @{ |
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*/ |
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#define RCC_CR_PLLRDY (1 << 25) |
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#define RCC_CR_PLLON (1 << 24) |
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#define RCC_CR_CSSON (1 << 19) |
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#define RCC_CR_HSEBYP (1 << 18) |
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#define RCC_CR_HSERDY (1 << 17) |
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#define RCC_CR_HSEON (1 << 16) |
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#define RCC_CR_HSIRDY (1 << 10) |
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#define RCC_CR_HSIKERON (1 << 9) |
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#define RCC_CR_HSION (1 << 8) |
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/**@}*/ |
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/** @defgroup rcc_icscr_values RCC_ICSCR values
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* @{ |
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*/ |
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#define RCC_ICSCR_HSITRIM_SHIFT 24 |
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#define RCC_ICSCR_HSITRIM_MASK 0x1f |
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#define RCC_ICSCR_HSICAL_SHIFT 16 |
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#define RCC_ICSCR_HSICAL_MASK 0xff |
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/**@}*/ |
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/** @defgroup rcc_cfgr_values RCC_CFGR values
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* @{ |
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*/ |
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/** @defgroup rcc_cfgr_mcopre MCOPRE MCO prescaler
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* @{ |
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*/ |
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#define RCC_CFGR_MCOPRE_DIV1 0 |
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#define RCC_CFGR_MCOPRE_DIV2 1 |
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#define RCC_CFGR_MCOPRE_DIV4 2 |
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#define RCC_CFGR_MCOPRE_DIV8 3 |
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#define RCC_CFGR_MCOPRE_DIV16 4 |
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/**@}*/ |
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#define RCC_CFGR_MCOPRE_SHIFT 28 |
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#define RCC_CFGR_MCOPRE_MASK 0x7 |
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/** @defgroup rcc_cfgr_mco MCO: Microcontroller clock output
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* @{ |
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*/ |
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#define RCC_CFGR_MCO_NOCLK 0x0 |
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#define RCC_CFGR_MCO_SYSCLK 0x1 |
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#define RCC_CFGR_MCO_HSI16 0x3 |
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#define RCC_CFGR_MCO_HSE 0x4 |
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#define RCC_CFGR_MCO_PLL 0x5 |
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#define RCC_CFGR_MCO_LSI 0x6 |
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#define RCC_CFGR_MCO_LSE 0x7 |
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#define RCC_CFGR_MCO_HSI48 0x8 |
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/**@}*/ |
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#define RCC_CFGR_MCO_SHIFT 24 |
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#define RCC_CFGR_MCO_MASK 0xf |
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/** @defgroup rcc_cfgr_pprex PPREx: APBx prescaler
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* @{ |
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*/ |
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#define RCC_CFGR_PPREx_NODIV 0x0 |
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#define RCC_CFGR_PPREx_DIV2 0x4 |
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#define RCC_CFGR_PPREx_DIV4 0x5 |
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#define RCC_CFGR_PPREx_DIV8 0x6 |
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#define RCC_CFGR_PPREx_DIV16 0x7 |
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/**@}*/ |
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#define RCC_CFGR_PPRE2_MASK 0x7 |
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#define RCC_CFGR_PPRE2_SHIFT 11 |
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#define RCC_CFGR_PPRE1_MASK 0x7 |
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#define RCC_CFGR_PPRE1_SHIFT 8 |
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/** @defgroup rcc_cfgr_hpre HPRE: AHB prescaler
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* @{ |
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*/ |
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#define RCC_CFGR_HPRE_NODIV 0x0 |
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#define RCC_CFGR_HPRE_DIV2 0x8 |
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#define RCC_CFGR_HPRE_DIV4 0x9 |
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#define RCC_CFGR_HPRE_DIV8 0xa |
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#define RCC_CFGR_HPRE_DIV16 0xb |
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#define RCC_CFGR_HPRE_DIV64 0xc |
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#define RCC_CFGR_HPRE_DIV128 0xd |
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#define RCC_CFGR_HPRE_DIV256 0xe |
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#define RCC_CFGR_HPRE_DIV512 0xf |
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/*@}*/ |
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#define RCC_CFGR_HPRE_MASK 0xf |
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#define RCC_CFGR_HPRE_SHIFT 4 |
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/** @defgroup rcc_cfgr_swx SW/SWS System clock switch (status)
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* @{ |
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*/ |
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#define RCC_CFGR_SWx_HSI16 0x1 |
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#define RCC_CFGR_SWx_HSE 0x2 |
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#define RCC_CFGR_SWx_PLL 0x3 |
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/**@}*/ |
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#define RCC_CFGR_SWS_MASK 0x3 |
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#define RCC_CFGR_SWS_SHIFT 2 |
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#define RCC_CFGR_SW_MASK 0x3 |
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#define RCC_CFGR_SW_SHIFT 0 |
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/**@}*/ |
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/** @defgroup rcc_pllcfgr_values RCC_PLLCFGR - PLL Configuration Register
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* @{ |
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*/ |
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#define RCC_CFGR_PLLPDIV_MASK 0x1f |
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#define RCC_CFGR_PLLPDIV_SHIFT 27 |
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#define RCC_PLLCFGR_PLLR_DIV2 0 |
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#define RCC_PLLCFGR_PLLR_DIV4 1 |
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#define RCC_PLLCFGR_PLLR_DIV6 2 |
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#define RCC_PLLCFGR_PLLR_DIV8 3 |
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#define RCC_PLLCFGR_PLLR_SHIFT 25 |
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#define RCC_PLLCFGR_PLLR_MASK 0x3 |
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#define RCC_PLLCFGR_PLLREN BIT24 |
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#define RCC_PLLCFGR_PLLQ_DIV2 0 |
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#define RCC_PLLCFGR_PLLQ_DIV4 1 |
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#define RCC_PLLCFGR_PLLQ_DIV6 2 |
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#define RCC_PLLCFGR_PLLQ_DIV8 3 |
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#define RCC_PLLCFGR_PLLQ_SHIFT 21 |
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#define RCC_PLLCFGR_PLLQ_MASK 0x3 |
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#define RCC_PLLCFGR_PLLQEN BIT20 |
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/* Division for PLLSAI3CLK, 0 == 7, 1 == 17 */ |
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#define RCC_PLLCFGR_PLLP BIT17 |
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#define RCC_PLLCFGR_PLLP_DIV7 0 |
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#define RCC_PLLCFGR_PLLP_DIV17 RCC_PLLCFGR_PLLP |
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#define RCC_PLLPEN (1 << 16) |
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/** @defgroup rcc_pllcfgr_plln RCC_PLLCFGR PLLN values
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* Allowed values 8 <= n <= 127, VCO output between 64 and 344 MHz |
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* @{*/ |
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#define RCC_PLLCFGR_PLLN_SHIFT 8 |
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#define RCC_PLLCFGR_PLLN_MASK 0x7f |
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/**@}*/ |
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/** @defgroup rcc_pllcfgr_pllm RCC_PLLCFGR PLLM values
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* Allowed values 1 <= m <= 16, VCO input between 2.66 and 8 MHz |
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* @{*/ |
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#define RCC_PLLCFGR_PLLM_SHIFT 0x4 |
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#define RCC_PLLCFGR_PLLM_MASK 0xf |
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#define RCC_PLLCFGR_PLLM(x) ((x)-1) |
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/**@}*/ |
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#define RCC_PLLCFGR_PLLSRC_NONE 0 |
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#define RCC_PLLCFGR_PLLSRC_HSI16 2 |
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#define RCC_PLLCFGR_PLLSRC_HSE 3 |
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#define RCC_PLLCFGR_PLLSRC_SHIFT 0 |
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#define RCC_PLLCFGR_PLLSRC_MASK 0x3 |
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/**@}*/ |
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/** @defgroup rcc_cier_values RCC_CIER - Clock interrupt enable register
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* @{ |
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*/ |
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#define RCC_CIER_HSI48RDYIE (1 << 10) |
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#define RCC_CIER_LSE_CSSIE (1 << 9) |
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/* OSC ready interrupt enable bits */ |
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#define RCC_CIER_PLLRDYIE (1 << 5) |
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#define RCC_CIER_HSERDYIE (1 << 4) |
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#define RCC_CIER_HSIRDYIE (1 << 3) |
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#define RCC_CIER_LSERDYIE (1 << 1) |
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#define RCC_CIER_LSIRDYIE (1 << 0) |
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/**@}*/ |
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/** @defgroup rcc_cifr_values RCC_CIFR - Clock interrupt flag register
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* @{ |
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*/ |
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#define RCC_CIFR_HSI48RDYF (1 << 10) |
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#define RCC_CIFR_LSECSSF (1 << 9) |
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#define RCC_CIFR_CSSF (1 << 8) |
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#define RCC_CIFR_PLLRDYF (1 << 5) |
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#define RCC_CIFR_HSERDYF (1 << 4) |
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#define RCC_CIFR_HSIRDYF (1 << 3) |
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#define RCC_CIFR_LSERDYF (1 << 1) |
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#define RCC_CIFR_LSIRDYF (1 << 0) |
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/**@}*/ |
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/** @defgroup rcc_cicr_values RCC_CICR - Clock interrupt clear register
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* @{ |
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*/ |
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#define RCC_CICR_HSI48RDYC (1 << 10) |
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#define RCC_CICR_LSECSSC (1 << 9) |
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#define RCC_CICR_CSSC (1 << 8) |
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#define RCC_CICR_PLLRDYC (1 << 5) |
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#define RCC_CICR_HSERDYC (1 << 4) |
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#define RCC_CICR_HSIRDYC (1 << 3) |
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#define RCC_CICR_LSERDYC (1 << 1) |
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#define RCC_CICR_LSIRDYC (1 << 0) |
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/**@}*/ |
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/** @defgroup rcc_ahbrstr_rst RCC_AHBxRSTR reset values (full set)
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@{*/ |
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/** @defgroup rcc_ahb1rstr_rst RCC_AHB1RSTR reset values
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@{*/ |
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#define RCC_AHB1RSTR_CRCRST (1 << 12) |
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#define RCC_AHB1RSTR_FLASHRST (1 << 8) |
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#define RCC_AHB1RSTR_FMACRST (1 << 4) |
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#define RCC_AHB1RSTR_CORDIC2RST (1 << 3) |
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#define RCC_AHB1RSTR_DMAMUX1RST (1 << 2) |
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#define RCC_AHB1RSTR_DMA2RST (1 << 1) |
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#define RCC_AHB1RSTR_DMA1RST (1 << 0) |
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/**@}*/ |
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/** @defgroup rcc_ahb2rstr_rst RCC_AHB2RSTR reset values
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@{*/ |
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#define RCC_AHB2RSTR_RNGRST (1 << 26) |
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#define RCC_AHB2RSTR_AESRST (1 << 24) |
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#define RCC_AHB2RSTR_DAC4RST (1 << 19) |
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#define RCC_AHB2RSTR_DAC3RST (1 << 18) |
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#define RCC_AHB2RSTR_DAC2RST (1 << 17) |
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#define RCC_AHB2RSTR_DAC1RST (1 << 16) |
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#define RCC_AHB2RSTR_ADC345RST (1 << 14) |
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#define RCC_AHB2RSTR_ADC12RST (1 << 13) |
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#define RCC_AHB2RSTR_GPIOGRST (1 << 6) |
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#define RCC_AHB2RSTR_GPIOFRST (1 << 5) |
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#define RCC_AHB2RSTR_GPIOERST (1 << 4) |
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#define RCC_AHB2RSTR_GPIODRST (1 << 3) |
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#define RCC_AHB2RSTR_GPIOCRST (1 << 2) |
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#define RCC_AHB2RSTR_GPIOBRST (1 << 1) |
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#define RCC_AHB2RSTR_GPIOARST (1 << 0) |
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/**@}*/ |
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/** @defgroup rcc_ahb3rstr_rst RCC_AHB3RSTR reset values
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@{*/ |
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#define RCC_AHB3RSTR_QSPIRST (1 << 8) |
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#define RCC_AHB3RSTR_FMCRST (1 << 0) |
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/**@}*/ |
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/**@}*/ |
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/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTRx reset values (full set)
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@{*/ |
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/** @defgroup rcc_apb1rstr1_rst RCC_APB1RSTR1 reset values
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@{*/ |
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#define RCC_APB1RSTR1_LPTIM1RST (1 << 31) |
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#define RCC_APB1RSTR1_I2C3RST (1 << 30) |
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#define RCC_APB1RSTR1_PWRRST (1 << 28) |
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#define RCC_APB1RSTR1_FDCANRST (1 << 25) |
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#define RCC_APB1RSTR1_USBRST (1 << 23) |
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#define RCC_APB1RSTR1_I2C2RST (1 << 22) |
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#define RCC_APB1RSTR1_I2C1RST (1 << 21) |
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#define RCC_APB1RSTR1_UART5RST (1 << 20) |
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#define RCC_APB1RSTR1_UART4RST (1 << 19) |
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#define RCC_APB1RSTR1_USART3RST (1 << 18) |
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#define RCC_APB1RSTR1_USART2RST (1 << 17) |
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#define RCC_APB1RSTR1_SPI3RST (1 << 15) |
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#define RCC_APB1RSTR1_SPI2RST (1 << 14) |
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#define RCC_APB1RSTR1_CRSRST (1 << 8) |
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#define RCC_APB1RSTR1_TIM7RST (1 << 5) |
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#define RCC_APB1RSTR1_TIM6RST (1 << 4) |
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#define RCC_APB1RSTR1_TIM5RST (1 << 3) |
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#define RCC_APB1RSTR1_TIM4RST (1 << 2) |
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#define RCC_APB1RSTR1_TIM3RST (1 << 1) |
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#define RCC_APB1RSTR1_TIM2RST (1 << 0) |
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/**@}*/ |
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/** @defgroup rcc_apb1rstr2_rst RCC_APB1RSTR2 reset values
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@{*/ |
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#define RCC_APB1RSTR2_UCPD1RST (1 << 8) |
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#define RCC_APB1RSTR2_I2C4RST (1 << 1) |
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#define RCC_APB1RSTR2_LPUART1RST (1 << 0) |
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/**@}*/ |
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/**@}*/ |
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/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values
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@{*/ |
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#define RCC_APB2RSTR_HRTIM1RST (1 << 26) |
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#define RCC_APB2RSTR_SAI1RST (1 << 21) |
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#define RCC_APB2RSTR_TIM20RST (1 << 20) |
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#define RCC_APB2RSTR_TIM17RST (1 << 18) |
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#define RCC_APB2RSTR_TIM16RST (1 << 17) |
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#define RCC_APB2RSTR_TIM15RST (1 << 16) |
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#define RCC_APB2RSTR_SPI4RST (1 << 15) |
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#define RCC_APB2RSTR_USART1RST (1 << 14) |
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#define RCC_APB2RSTR_TIM8RST (1 << 13) |
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#define RCC_APB2RSTR_SPI1RST (1 << 12) |
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#define RCC_APB2RSTR_TIM1RST (1 << 11) |
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#define RCC_APB2RSTR_SYSCFGRST (1 << 0) |
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/**@}*/ |
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/** @defgroup rcc_ahbenr_en RCC_AHBxENR enable values (full set)
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*@{*/ |
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/** @defgroup rcc_ahb1enr_en RCC_AHB1ENR enable values
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*@{*/ |
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#define RCC_AHB1ENR_CRCEN (1 << 12) |
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#define RCC_AHB1ENR_FLASHEN (1 << 8) |
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#define RCC_AHB1ENR_FMACEN (1 << 4) |
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#define RCC_AHB1ENR_CORDICEN (1 << 3) |
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#define RCC_AHB1ENR_DMAMUX1EN (1 << 2) |
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#define RCC_AHB1ENR_DMA2EN (1 << 1) |
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#define RCC_AHB1ENR_DMA1EN (1 << 0) |
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/**@}*/ |
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/** @defgroup rcc_ahb2enr_en RCC_AHB2ENR enable values
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*@{*/ |
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#define RCC_AHB2ENR_RNGEN (1 << 26) |
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#define RCC_AHB2ENR_AESEN (1 << 24) |
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#define RCC_AHB2ENR_DAC4EN (1 << 19) |
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#define RCC_AHB2ENR_DAC3EN (1 << 18) |
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#define RCC_AHB2ENR_DAC2EN (1 << 17) |
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#define RCC_AHB2ENR_DAC1EN (1 << 16) |
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#define RCC_AHB2ENR_ADC345EN (1 << 14) |
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#define RCC_AHB2ENR_ADC12EN (1 << 13) |
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#define RCC_AHB2ENR_GPIOGEN (1 << 6) |
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#define RCC_AHB2ENR_GPIOFEN (1 << 5) |
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#define RCC_AHB2ENR_GPIOEEN (1 << 4) |
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#define RCC_AHB2ENR_GPIODEN (1 << 3) |
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#define RCC_AHB2ENR_GPIOCEN (1 << 2) |
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#define RCC_AHB2ENR_GPIOBEN (1 << 1) |
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#define RCC_AHB2ENR_GPIOAEN (1 << 0) |
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/**@}*/ |
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/** @defgroup rcc_ahb3enr_en RCC_AHB3ENR enable values
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*@{*/ |
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#define RCC_AHB3ENR_QSPIEN (1 << 8) |
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#define RCC_AHB3ENR_FMCEN (1 << 0) |
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/**@}*/ |
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/**@}*/ |
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/** @defgroup rcc_apb1enr_en RCC_APB1ENRx enable values (full set)
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*@{*/ |
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/** @defgroup rcc_apb1enr1_en RCC_APB1ENR1 enable values
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*@{*/ |
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#define RCC_APB1ENR1_LPTIM1EN (1 << 31) |
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#define RCC_APB1ENR1_I2C3EN (1 << 30) |
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#define RCC_APB1ENR1_PWREN (1 << 28) |
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#define RCC_APB1ENR1_FDCANEN (1 << 25) |
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#define RCC_APB1ENR1_USBEN (1 << 23) |
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#define RCC_APB1ENR1_I2C2EN (1 << 22) |
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#define RCC_APB1ENR1_I2C1EN (1 << 21) |
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#define RCC_APB1ENR1_UART5EN (1 << 20) |
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#define RCC_APB1ENR1_UART4EN (1 << 19) |
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#define RCC_APB1ENR1_USART3EN (1 << 18) |
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#define RCC_APB1ENR1_USART2EN (1 << 17) |
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#define RCC_APB1ENR1_SPI3EN (1 << 15) |
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#define RCC_APB1ENR1_SPI2EN (1 << 14) |
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#define RCC_APB1ENR1_WWDGEN (1 << 11) |
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#define RCC_APB1ENR1_RTCAPBEN (1 << 10) |
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#define RCC_APB1ENR1_CRSEN (1 << 8) |
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#define RCC_APB1ENR1_TIM7EN (1 << 5) |
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#define RCC_APB1ENR1_TIM6EN (1 << 4) |
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#define RCC_APB1ENR1_TIM5EN (1 << 3) |
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#define RCC_APB1ENR1_TIM4EN (1 << 2) |
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#define RCC_APB1ENR1_TIM3EN (1 << 1) |
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#define RCC_APB1ENR1_TIM2EN (1 << 0) |
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/*@}*/ |
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/** @defgroup rcc_apb1enr2_en RCC_APB1ENR2 enable values
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*@{*/ |
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#define RCC_APB1ENR2_UCPD1EN (1 << 8) |
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#define RCC_APB1ENR2_I2C4EN (1 << 1) |
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#define RCC_APB1ENR2_LPUART1EN (1 << 0) |
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/*@}*/ |
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/*@}*/ |
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/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values
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*@{*/ |
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#define RCC_APB2ENR_HRTIM1EN (1 << 26) |
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#define RCC_APB2ENR_SAI1EN (1 << 21) |
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#define RCC_APB2ENR_TIM20EN (1 << 20) |
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#define RCC_APB2ENR_TIM17EN (1 << 18) |
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#define RCC_APB2ENR_TIM16EN (1 << 17) |
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#define RCC_APB2ENR_TIM15EN (1 << 16) |
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#define RCC_APB2ENR_SPI4EN (1 << 15) |
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#define RCC_APB2ENR_USART1EN (1 << 14) |
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#define RCC_APB2ENR_TIM8EN (1 << 13) |
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#define RCC_APB2ENR_SPI1EN (1 << 12) |
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#define RCC_APB2ENR_TIM1EN (1 << 11) |
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#define RCC_APB2ENR_SYSCFGEN (1 << 0) |
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/**@}*/ |
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/** @defgroup rcc_ahb1smenr_values RCC_AHB1SMENR - AHB1 periph clock in sleep mode
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* @{ |
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*/ |
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#define RCC_AHB1SMENR_CRCSMEN (1 << 12) |
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#define RCC_AHB1SMENR_SRAM1SMEN (1 << 9) |
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#define RCC_AHB1SMENR_FLASHSMEN (1 << 8) |
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#define RCC_AHB1SMENR_FMACSMEN (1 << 4) |
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#define RCC_AHB1SMENR_CORFDICSMEN (1 << 3) |
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#define RCC_AHB1SMENR_DMAMUX1SMEN (1 << 2) |
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#define RCC_AHB1SMENR_DMA2SMEN (1 << 1) |
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#define RCC_AHB1SMENR_DMA1SMEN (1 << 0) |
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/**@}*/ |
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/** @defgroup rcc_ahb2smenr RCC_AHB2SMENR - AHB2 periph clock in sleep mode
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* @{ |
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*/ |
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#define RCC_AHB2SMENR_RNGSMEN (1 << 26) |
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#define RCC_AHB2SMENR_AESSMEN (1 << 24) |
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#define RCC_AHB2SMENR_DAC4SMEN (1 << 19) |
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#define RCC_AHB2SMENR_DAC3SMEN (1 << 18) |
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#define RCC_AHB2SMENR_DAC2SMEN (1 << 17) |
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#define RCC_AHB2SMENR_DAC1SMEN (1 << 16) |
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#define RCC_AHB2SMENR_ADC345SMEN (1 << 14) |
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#define RCC_AHB2SMENR_ADC12SMEN (1 << 13) |
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#define RCC_AHB2SMENR_SRAM2SMEN (1 << 10) |
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#define RCC_AHB2SMENR_CCMSRAMSMEN (1 << 9) |
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#define RCC_AHB2SMENR_GPIOGSMEN (1 << 6) |
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#define RCC_AHB2SMENR_GPIOFSMEN (1 << 5) |
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#define RCC_AHB2SMENR_GPIOESMEN (1 << 4) |
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#define RCC_AHB2SMENR_GPIODSMEN (1 << 3) |
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#define RCC_AHB2SMENR_GPIOCSMEN (1 << 2) |
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#define RCC_AHB2SMENR_GPIOBSMEN (1 << 1) |
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#define RCC_AHB2SMENR_GPIOASMEN (1 << 0) |
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/**@}*/ |
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/** @defgroup rcc_ahb3smenr RCC_AHB3SMENR - AHB3 periph clock in sleep mode
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* @{ |
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*/ |
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#define RCC_AHB3SMENR_QSPISMEN (1 << 8) |
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#define RCC_AHB3SMENR_FMCSMEN (1 << 0) |
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/**@}*/ |
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/** @defgroup rcc_apb1smenr1 RCC_APB1SMENR1 - APB1 periph clock in sleep mode
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* @{ |
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*/ |
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#define RCC_APB1SMENR1_LPTIM1SMEN (1 << 31) |
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#define RCC_APB1SMENR1_I2C3SMEN (1 << 30) |
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#define RCC_APB1SMENR1_PWRSMEN (1 << 28) |
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#define RCC_APB1SMENR1_FDCANSMEN (1 << 25) |
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#define RCC_APB1SMENR1_USBSMEN (1 << 23) |
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#define RCC_APB1SMENR1_I2C2SMEN (1 << 22) |
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#define RCC_APB1SMENR1_I2C1SMEN (1 << 21) |
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#define RCC_APB1SMENR1_UART5SMEN (1 << 20) |
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#define RCC_APB1SMENR1_UART4SMEN (1 << 19) |
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#define RCC_APB1SMENR1_USART3SMEN (1 << 18) |
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#define RCC_APB1SMENR1_USART2SMEN (1 << 17) |
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#define RCC_APB1SMENR1_SPI3SMEN (1 << 15) |
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#define RCC_APB1SMENR1_SPI2SMEN (1 << 14) |
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#define RCC_APB1SMENR1_WWDGSMEN (1 << 11) |
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#define RCC_APB1SMENR1_RTCAPBSMEN (1 << 10) |
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#define RCC_APB1SMENR1_TIM7SMEN (1 << 5) |
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#define RCC_APB1SMENR1_TIM6SMEN (1 << 4) |
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#define RCC_APB1SMENR1_TIM5SMEN (1 << 3) |
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#define RCC_APB1SMENR1_TIM4SMEN (1 << 2) |
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#define RCC_APB1SMENR1_TIM3SMEN (1 << 1) |
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#define RCC_APB1SMENR1_TIM2SMEN (1 << 0) |
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/**@}*/ |
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/** @defgroup rcc_apb1smenr2 RCC_APB1SMENR2 - APB1 periph clock in sleep mode
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* @{ |
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*/ |
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#define RCC_APB1SMENR2_UCPD1SMEN (1 << 8) |
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#define RCC_APB1SMENR2_I2C4SMEN (1 << 1) |
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#define RCC_APB1SMENR2_LPUART1SMEN (1 << 0) |
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/**@}*/ |
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/** @defgroup rcc_apb2smenr RCC_APB2SMENR - APB2 periph clock in sleep mode
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|
* @{ |
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*/ |
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#define RCC_APB2SMENR_HRTIM1SMEN (1 << 26) |
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#define RCC_APB2SMENR_SAI1SMEN (1 << 21) |
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#define RCC_APB2SMENR_TIM20SMEN (1 << 20) |
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#define RCC_APB2SMENR_TIM17SMEN (1 << 18) |
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#define RCC_APB2SMENR_TIM16SMEN (1 << 17) |
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#define RCC_APB2SMENR_TIM15SMEN (1 << 16) |
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#define RCC_APB2SMENR_SPI4SMEN (1 << 15) |
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#define RCC_APB2SMENR_USART1SMEN (1 << 14) |
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#define RCC_APB2SMENR_TIM8SMEN (1 << 13) |
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#define RCC_APB2SMENR_SPI1SMEN (1 << 12) |
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#define RCC_APB2SMENR_TIM1SMEN (1 << 11) |
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#define RCC_APB2SMENR_SYSCFGSMEN (1 << 0) |
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/**@}*/ |
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/** @defgroup rcc_ccipr_values RCC_CCIPR - Peripherals independent clock config register
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|
* @{ |
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*/ |
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/* all fields are 2 bits */ |
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#define RCC_CCIPR_SEL_MASK 0x3 |
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#define RCC_CCIPR_ADC345_NONE 0 |
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#define RCC_CCIPR_ADC345_PLLP 1 |
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#define RCC_CCIPR_ADC345_SYS 2 |
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#define RCC_CCIPR_ADC345_SHIFT 30 |
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#define RCC_CCIPR_ADC12_NONE 0 |
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#define RCC_CCIPR_ADC12_PLLP 1 |
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#define RCC_CCIPR_ADC12_SYS 2 |
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#define RCC_CCIPR_ADC12_SHIFT 28 |
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#define RCC_CCIPR_CLK48_HSI48 0 |
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#define RCC_CCIPR_CLK48_PLLQ 2 |
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#define RCC_CCIPR_CLK48_SHIFT 26 |
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#define RCC_CCIPR_FDCAN_HSE 0 |
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#define RCC_CCIPR_FDCAN_PLLQ 1 |
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#define RCC_CCIPR_FDCAN_PCLK 2 |
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#define RCC_CCIPR_FDCAN_SHIFT 24 |
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#define RCC_CCIPR_I2S23_SYS 0 |
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#define RCC_CCIPR_I2S23_PLLQ 1 |
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#define RCC_CCIPR_I2S23_EXT 2 |
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#define RCC_CCIPR_I2S23_SHI16 3 |
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#define RCC_CCIPR_I2S23_SHIFT 22 |
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#define RCC_CCIPR_SAI1_SYS 0 |
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#define RCC_CCIPR_SAI1_PLLQ 1 |
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#define RCC_CCIPR_SAI1_EXT 2 |
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#define RCC_CCIPR_SAI1_HSI16 3 |
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#define RCC_CCIPR_SAI1_SHIFT 20 |
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#define RCC_CCIPR_LPTIM1_PCLK 0 |
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#define RCC_CCIPR_LPTIM1_LSI 1 |
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#define RCC_CCIPR_LPTIM1_HSI16 2 |
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#define RCC_CCIPR_LPTIM1_LSE 3 |
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#define RCC_CCIPR_LPTIM1SEL_SHIFT 18 |
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#define RCC_CCIPR_I2Cx_PCLK 0 |
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#define RCC_CCIPR_I2Cx_SYS 1 |
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#define RCC_CCIPR_I2Cx_HSI16 2 |
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#define RCC_CCIPR_I2C3_SHIFT 16 |
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#define RCC_CCIPR_I2C2_SHIFT 14 |
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#define RCC_CCIPR_I2C1_SHIFT 12 |
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#define RCC_CCIPR_LPUART1_PCLK 0 |
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#define RCC_CCIPR_LPUART1_SYS 1 |
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#define RCC_CCIPR_LPUART1_HSI16 2 |
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#define RCC_CCIPR_LPUART1_LSE 3 |
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#define RCC_CCIPR_LPUART1SEL_SHIFT 10 |
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#define RCC_CCIPR_USARTx_PCLK 0 |
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#define RCC_CCIPR_USARTx_SYS 1 |
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#define RCC_CCIPR_USARTx_HSI16 2 |
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|
#define RCC_CCIPR_USARTx_LSE 3 |
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#define RCC_CCIPR_UARTx_PCLK RCC_CCIPR_USARTx_PCLK |
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#define RCC_CCIPR_UARTx_SYS RCC_CCIPR_USARTx_SYS |
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#define RCC_CCIPR_UARTx_HSI16 RCC_CCIPR_USARTx_HSI16 |
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#define RCC_CCIPR_UARTx_LSE RCC_CCIPR_USARTx_LSE |
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#define RCC_CCIPR_UART5_SHIFT 8 |
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#define RCC_CCIPR_UART4_SHIFT 6 |
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#define RCC_CCIPR_USART3_SHIFT 4 |
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#define RCC_CCIPR_USART2_SHIFT 2 |
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#define RCC_CCIPR_USART1_SHIFT 0 |
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/**@}*/ |
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/** defgroup rcc_ccipr2_values RCC_CCIPR2 - Peripherals independent clock config register 2
|
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|
* @{ |
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|
*/ |
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|
#define RCC_CCIPR2_QSPI_SYS 0 |
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#define RCC_CCIPR2_QSPI_HSI16 1 |
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#define RCC_CCIPR2_QSPI_PLLQ 2 |
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#define RCC_CCIPR2_QSPI_SHIFT 20 |
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#define RCC_CCIPR2_I2C4_PCLK 0 |
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#define RCC_CCIPR2_I2C4_SYS 1 |
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#define RCC_CCIPR2_I2C4_HSI16 2 |
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#define RCC_CCIPR2_I2C4_SHIFT 0 |
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/**@}*/ |
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/** @defgroup rcc_bdcr_values RCC_BDCR - Backup domain control register
|
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* @{ |
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*/ |
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#define RCC_BDCR_LSCOSEL (1 << 25) |
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#define RCC_BDCR_LSCOEN (1 << 24) |
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#define RCC_BDCR_BDRST (1 << 16) |
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#define RCC_BDCR_RTCEN (1 << 15) |
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#define RCC_BDCR_RTCSEL_NONE 0 |
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#define RCC_BDCR_RTCSEL_LSE 1 |
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#define RCC_BDCR_RTCSEL_LSI 2 |
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#define RCC_BDCR_RTCSEL_HSEDIV32 3 |
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#define RCC_BDCR_RTCSEL_SHIFT 8 |
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#define RCC_BDCR_RTCSEL_MASK 0x3 |
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#define RCC_BDCR_LSECSSD (1 << 6) |
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#define RCC_BDCR_LSECSSON (1 << 5) |
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#define RCC_BDCR_LSEDRV_LOW 0 |
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#define RCC_BDCR_LSEDRV_MEDLOW 1 |
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#define RCC_BDCR_LSEDRV_MEDHIGH 2 |
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#define RCC_BDCR_LSEDRV_HIGH 3 |
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#define RCC_BDCR_LSEDRV_SHIFT 3 |
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#define RCC_BDCR_LSEDRV_MASK 0x3 |
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#define RCC_BDCR_LSEBYP (1 << 2) |
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#define RCC_BDCR_LSERDY (1 << 1) |
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#define RCC_BDCR_LSEON (1 << 0) |
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/**@}*/ |
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/** @defgroup rcc_csr_values RCC_CSR - Control/Status register
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* @{ |
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*/ |
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#define RCC_CSR_LPWRRSTF (1 << 31) |
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#define RCC_CSR_WWDGRSTF (1 << 30) |
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#define RCC_CSR_IWDGRSTF (1 << 29) |
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#define RCC_CSR_SFTRSTF (1 << 28) |
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#define RCC_CSR_BORRSTF (1 << 27) |
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#define RCC_CSR_PINRSTF (1 << 26) |
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#define RCC_CSR_OBLRSTF (1 << 25) |
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#define RCC_CSR_RMVF (1 << 23) |
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#define RCC_CSR_RESET_FLAGS (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF |\ |
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RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_BORRSTF |\ |
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RCC_CSR_PINRSTF | RCC_CSR_OBLRSTF) |
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#define RCC_CSR_LSIRDY (1 << 1) |
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#define RCC_CSR_LSION (1 << 0) |
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/**@}*/ |
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/** @defgroup rcc_crrcr RCC_CRRCR Clock Recovery RC register
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* @{ |
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*/ |
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#define RCC_CRRCR_HSI48VAL_MASK 0x1ff |
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#define RCC_CRRCR_HSI48VAL_SHIFT 7 |
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#define RCC_CRRCR_HSI48RDY BIT1 |
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#define RCC_CRRCR_HSI48ON BIT0 |
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/**@}*/ |
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/* --- Variable definitions ------------------------------------------------ */ |
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extern uint32_t rcc_ahb_frequency; |
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extern uint32_t rcc_apb1_frequency; |
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extern uint32_t rcc_apb2_frequency; |
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/* --- Function prototypes ------------------------------------------------- */ |
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enum rcc_osc { |
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RCC_PLL, RCC_HSE, RCC_HSI16, RCC_LSE, RCC_LSI, RCC_HSI48 |
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}; |
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#define _REG_BIT(base, bit) (((base) << 5) + (bit)) |
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enum rcc_periph_clken { |
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/* AHB1 peripherals */ |
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RCC_CRC = _REG_BIT(0x48, 12), |
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RCC_FLASH = _REG_BIT(0x48, 8), |
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RCC_FMAC = _REG_BIT(0x48, 4), |
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RCC_CORDIC = _REG_BIT(0x48, 3), |
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RCC_DMAMUX1 = _REG_BIT(0x48, 2), |
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RCC_DMA2 = _REG_BIT(0x48, 1), |
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RCC_DMA1 = _REG_BIT(0x48, 0), |
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/* AHB2 peripherals */ |
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RCC_RNG = _REG_BIT(0x4c, 26), |
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RCC_AES = _REG_BIT(0x4c, 24), |
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RCC_DAC4 = _REG_BIT(0x4c, 19), |
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RCC_DAC3 = _REG_BIT(0x4c, 18), |
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RCC_DAC2 = _REG_BIT(0x4c, 17), |
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RCC_DAC1 = _REG_BIT(0x4c, 16), |
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RCC_ADC345 = _REG_BIT(0x4c, 14), |
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RCC_ADC12 = _REG_BIT(0x4c, 13), |
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RCC_ADC1 = _REG_BIT(0x4c, 13), /* Compatibility */ |
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RCC_GPIOG = _REG_BIT(0x4c, 6), |
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RCC_GPIOF = _REG_BIT(0x4c, 5), |
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RCC_GPIOE = _REG_BIT(0x4c, 4), |
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RCC_GPIOD = _REG_BIT(0x4c, 3), |
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RCC_GPIOC = _REG_BIT(0x4c, 2), |
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RCC_GPIOB = _REG_BIT(0x4c, 1), |
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RCC_GPIOA = _REG_BIT(0x4c, 0), |
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/* AHB3 peripherals */ |
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RCC_QSPI = _REG_BIT(0x50, 8), |
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RCC_FMC = _REG_BIT(0x50, 0), |
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/* APB1 peripherals */ |
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RCC_LPTIM1 = _REG_BIT(0x58, 31), |
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RCC_I2C3 = _REG_BIT(0x58, 30), |
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RCC_PWR = _REG_BIT(0x58, 28), |
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RCC_FDCAN = _REG_BIT(0x58, 25), |
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RCC_USB = _REG_BIT(0x58, 23), |
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RCC_I2C2 = _REG_BIT(0x58, 22), |
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RCC_I2C1 = _REG_BIT(0x58, 21), |
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RCC_UART5 = _REG_BIT(0x58, 20), |
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RCC_UART4 = _REG_BIT(0x58, 19), |
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RCC_USART3 = _REG_BIT(0x58, 18), |
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RCC_USART2 = _REG_BIT(0x58, 17), |
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RCC_SPI3 = _REG_BIT(0x58, 15), |
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RCC_SPI2 = _REG_BIT(0x58, 14), |
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RCC_WWDG = _REG_BIT(0x58, 11), |
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RCC_RTCAPB = _REG_BIT(0x58, 10), |
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RCC_CRS = _REG_BIT(0x58, 8), |
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RCC_TIM7 = _REG_BIT(0x58, 5), |
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RCC_TIM6 = _REG_BIT(0x58, 4), |
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RCC_TIM5 = _REG_BIT(0x58, 3), |
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RCC_TIM4 = _REG_BIT(0x58, 2), |
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RCC_TIM3 = _REG_BIT(0x58, 1), |
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RCC_TIM2 = _REG_BIT(0x58, 0), |
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/* apb1-2 */ |
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RCC_UCPD1 = _REG_BIT(0x5c, 8), |
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RCC_I2C4 = _REG_BIT(0x5c, 1), |
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RCC_LPUART1 = _REG_BIT(0x5c, 0), |
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/* APB2 peripherals */ |
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RCC_HRTIM1 = _REG_BIT(0x60, 26), |
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RCC_SAI1 = _REG_BIT(0x60, 21), |
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RCC_TIM20 = _REG_BIT(0x60, 20), |
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RCC_TIM17 = _REG_BIT(0x60, 18), |
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RCC_TIM16 = _REG_BIT(0x60, 17), |
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RCC_TIM15 = _REG_BIT(0x60, 16), |
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RCC_SPI4 = _REG_BIT(0x60, 15), |
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RCC_USART1 = _REG_BIT(0x60, 14), |
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RCC_TIM8 = _REG_BIT(0x60, 13), |
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RCC_SPI1 = _REG_BIT(0x60, 12), |
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RCC_TIM1 = _REG_BIT(0x60, 11), |
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RCC_SYSCFG = _REG_BIT(0x60, 0), |
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/* AHB1 peripherals in sleep mode */ |
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SCC_CRC = _REG_BIT(0x68, 12), |
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SCC_SRAM1 = _REG_BIT(0x68, 9), |
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SCC_FLASH = _REG_BIT(0x68, 8), |
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SCC_FMAC = _REG_BIT(0x68, 4), |
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SCC_CORDIC = _REG_BIT(0x68, 3), |
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SCC_DMAMUX1 = _REG_BIT(0x68, 2), |
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SCC_DMA2 = _REG_BIT(0x68, 1), |
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SCC_DMA1 = _REG_BIT(0x68, 0), |
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/* AHB2 peripherals in sleep mode */ |
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SCC_RNG = _REG_BIT(0x6c, 26), |
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SCC_AES = _REG_BIT(0x6c, 24), |
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SCC_DAC4 = _REG_BIT(0x6c, 19), |
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SCC_DAC3 = _REG_BIT(0x6c, 18), |
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SCC_DAC2 = _REG_BIT(0x6c, 17), |
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SCC_DAC1 = _REG_BIT(0x6c, 16), |
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SCC_ADC345 = _REG_BIT(0x6c, 14), |
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SCC_ADC12 = _REG_BIT(0x6c, 13), |
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SCC_ADC1 = _REG_BIT(0x6c, 13), /* Compatibility */ |
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SCC_CCMSRAM = _REG_BIT(0x6c, 10), |
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SCC_SRAM2 = _REG_BIT(0x6c, 9), |
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SCC_GPIOG = _REG_BIT(0x6c, 6), |
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SCC_GPIOF = _REG_BIT(0x6c, 5), |
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SCC_GPIOE = _REG_BIT(0x6c, 4), |
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SCC_GPIOD = _REG_BIT(0x6c, 3), |
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SCC_GPIOC = _REG_BIT(0x6c, 2), |
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SCC_GPIOB = _REG_BIT(0x6c, 1), |
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SCC_GPIOA = _REG_BIT(0x6c, 0), |
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/* AHB3 peripherals in sleep mode */ |
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SCC_QSPI = _REG_BIT(0x70, 8), |
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SCC_FMC = _REG_BIT(0x70, 0), |
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/* APB1 peripherals in sleep mode */ |
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SCC_LPTIM1 = _REG_BIT(0x58, 31), |
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SCC_I2C3 = _REG_BIT(0x58, 30), |
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SCC_PWR = _REG_BIT(0x58, 28), |
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SCC_FDCAN = _REG_BIT(0x58, 25), |
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SCC_USB = _REG_BIT(0x58, 23), |
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SCC_I2C2 = _REG_BIT(0x58, 22), |
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SCC_I2C1 = _REG_BIT(0x58, 21), |
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SCC_UART5 = _REG_BIT(0x58, 20), |
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SCC_UART4 = _REG_BIT(0x58, 19), |
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SCC_USART3 = _REG_BIT(0x58, 18), |
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SCC_USART2 = _REG_BIT(0x58, 17), |
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SCC_SPI3 = _REG_BIT(0x58, 15), |
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SCC_SPI2 = _REG_BIT(0x58, 14), |
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SCC_WWDG = _REG_BIT(0x58, 11), |
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SCC_RTCAPB = _REG_BIT(0x58, 10), |
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SCC_CRS = _REG_BIT(0x58, 8), |
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SCC_TIM7 = _REG_BIT(0x58, 5), |
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SCC_TIM6 = _REG_BIT(0x58, 4), |
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SCC_TIM5 = _REG_BIT(0x58, 3), |
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SCC_TIM4 = _REG_BIT(0x58, 2), |
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SCC_TIM3 = _REG_BIT(0x58, 1), |
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SCC_TIM2 = _REG_BIT(0x58, 0), |
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/* apb1-2 */ |
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SCC_UCPD1 = _REG_BIT(0x5c, 8), |
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SCC_I2C4 = _REG_BIT(0x5c, 1), |
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SCC_LPUART1 = _REG_BIT(0x5c, 0), |
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/* APB2 peripherals in sleep mode */ |
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SCC_HRTIM1 = _REG_BIT(0x60, 26), |
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SCC_SAI1 = _REG_BIT(0x60, 21), |
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SCC_TIM20 = _REG_BIT(0x60, 20), |
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SCC_TIM17 = _REG_BIT(0x60, 18), |
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SCC_TIM16 = _REG_BIT(0x60, 17), |
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SCC_TIM15 = _REG_BIT(0x60, 16), |
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SCC_SPI4 = _REG_BIT(0x60, 15), |
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SCC_USART1 = _REG_BIT(0x60, 14), |
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SCC_TIM8 = _REG_BIT(0x60, 13), |
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SCC_SPI1 = _REG_BIT(0x60, 12), |
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SCC_TIM1 = _REG_BIT(0x60, 11), |
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SCC_SYSCFG = _REG_BIT(0x60, 0), |
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}; |
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enum rcc_periph_rst { |
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/* AHB1 peripherals */ |
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RST_CRC = _REG_BIT(0x28, 12), |
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RST_FLASH = _REG_BIT(0x28, 8), |
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RST_FMAC = _REG_BIT(0x28, 4), |
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RST_CORDIC = _REG_BIT(0x28, 3), |
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RST_DMAMUX1 = _REG_BIT(0x28, 2), |
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RST_DMA2 = _REG_BIT(0x28, 1), |
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RST_DMA1 = _REG_BIT(0x28, 0), |
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/* AHB2 peripherals */ |
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RST_RNG = _REG_BIT(0x2c, 26), |
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RST_AES = _REG_BIT(0x2c, 24), |
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RST_DAC4 = _REG_BIT(0x2c, 19), |
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RST_DAC3 = _REG_BIT(0x2c, 18), |
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RST_DAC2 = _REG_BIT(0x2c, 17), |
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RST_DAC1 = _REG_BIT(0x2c, 16), |
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RST_ADC345 = _REG_BIT(0x2c, 14), |
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RST_ADC12 = _REG_BIT(0x2c, 13), |
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RST_ADC1 = _REG_BIT(0x2c, 13), /* Compatibility */ |
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RST_GPIOG = _REG_BIT(0x2c, 6), |
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RST_GPIOF = _REG_BIT(0x2c, 5), |
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RST_GPIOE = _REG_BIT(0x2c, 4), |
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RST_GPIOD = _REG_BIT(0x2c, 3), |
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RST_GPIOC = _REG_BIT(0x2c, 2), |
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RST_GPIOB = _REG_BIT(0x2c, 1), |
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RST_GPIOA = _REG_BIT(0x2c, 0), |
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/* AHB3 peripherals */ |
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RST_QSPI = _REG_BIT(0x30, 8), |
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RST_FMC = _REG_BIT(0x30, 0), |
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/* APB1 peripherals */ |
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RST_LPTIM1 = _REG_BIT(0x38, 31), |
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RST_I2C3 = _REG_BIT(0x38, 30), |
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RST_PWR = _REG_BIT(0x38, 28), |
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RST_FDCAN = _REG_BIT(0x38, 25), |
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RST_USB = _REG_BIT(0x38, 23), |
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RST_I2C2 = _REG_BIT(0x38, 22), |
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RST_I2C1 = _REG_BIT(0x38, 21), |
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RST_UART5 = _REG_BIT(0x38, 20), |
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RST_UART4 = _REG_BIT(0x38, 19), |
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RST_USART3 = _REG_BIT(0x38, 18), |
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RST_USART2 = _REG_BIT(0x38, 17), |
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RST_SPI3 = _REG_BIT(0x38, 15), |
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RST_SPI2 = _REG_BIT(0x38, 14), |
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RST_CRS = _REG_BIT(0x38, 8), |
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RST_TIM7 = _REG_BIT(0x38, 5), |
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RST_TIM6 = _REG_BIT(0x38, 4), |
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RST_TIM5 = _REG_BIT(0x38, 3), |
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RST_TIM4 = _REG_BIT(0x38, 2), |
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RST_TIM3 = _REG_BIT(0x38, 1), |
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RST_TIM2 = _REG_BIT(0x38, 0), |
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/* apb1-2 */ |
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RST_UCPD1 = _REG_BIT(0x3c, 8), |
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RST_I2C4 = _REG_BIT(0x3c, 1), |
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RST_LPUART1 = _REG_BIT(0x3c, 0), |
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/* APB2 peripherals */ |
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RST_HRTIM1 = _REG_BIT(0x40, 26), |
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RST_SAI1 = _REG_BIT(0x40, 21), |
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RST_TIM20 = _REG_BIT(0x40, 20), |
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RST_TIM17 = _REG_BIT(0x40, 18), |
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RST_TIM16 = _REG_BIT(0x40, 17), |
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RST_TIM15 = _REG_BIT(0x40, 16), |
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RST_SPI4 = _REG_BIT(0x40, 15), |
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RST_USART1 = _REG_BIT(0x40, 14), |
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RST_TIM8 = _REG_BIT(0x40, 13), |
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RST_SPI1 = _REG_BIT(0x40, 12), |
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RST_TIM1 = _REG_BIT(0x40, 11), |
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RST_SYSCFG = _REG_BIT(0x40, 0), |
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}; |
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#include <libopencm3/stm32/common/rcc_common_all.h> |
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BEGIN_DECLS |
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END_DECLS |
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/**@}*/ |
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#endif |
Karl Palsson
5 years ago